Cost-efficient partially-parallel irregular LDPC decoder with message passing schedule

Xing Li, Yuta Abe, Kazunori Shimizu, Zhen Qiu, Takeshi Ikenaga, Satoshi Goto

研究成果: Conference contribution

7 引用 (Scopus)

抜粋

This paper proposes an improved Message Passing schedule for irregular LDPC decoder. Redundant memory accesses and column operations are removed by utilizing the characteristics of partial-parallel irregular LDPC decoding algorithm. As a result, the memory access frequency and hardware cost are efficiently reduced. According to the experimental results and comparison with existing work, proposed decoder provides a 30% hardware area reduction and a 36% power consumption saving with the same error correcting performance.

元の言語English
ホスト出版物のタイトル2007 International Symposium on Integrated Circuits, ISIC
ページ508-511
ページ数4
DOI
出版物ステータスPublished - 2007 12 1
イベント2007 International Symposium on Integrated Circuits, ISIC - Singapore, Singapore
継続期間: 2007 9 262007 9 28

出版物シリーズ

名前2007 International Symposium on Integrated Circuits, ISIC

Conference

Conference2007 International Symposium on Integrated Circuits, ISIC
Singapore
Singapore
期間07/9/2607/9/28

ASJC Scopus subject areas

  • Hardware and Architecture
  • Electrical and Electronic Engineering

フィンガープリント Cost-efficient partially-parallel irregular LDPC decoder with message passing schedule' の研究トピックを掘り下げます。これらはともに一意のフィンガープリントを構成します。

  • これを引用

    Li, X., Abe, Y., Shimizu, K., Qiu, Z., Ikenaga, T., & Goto, S. (2007). Cost-efficient partially-parallel irregular LDPC decoder with message passing schedule. : 2007 International Symposium on Integrated Circuits, ISIC (pp. 508-511). [4441910] (2007 International Symposium on Integrated Circuits, ISIC). https://doi.org/10.1109/ISICIR.2007.4441910