Cost-efficient partially-parallel irregular LDPC decoder with message passing schedule

Xing Li, Yuta Abe, Kazunori Shimizu, Zhen Qiu, Takeshi Ikenaga, Satoshi Goto

研究成果: Conference contribution

7 被引用数 (Scopus)

抄録

This paper proposes an improved Message Passing schedule for irregular LDPC decoder. Redundant memory accesses and column operations are removed by utilizing the characteristics of partial-parallel irregular LDPC decoding algorithm. As a result, the memory access frequency and hardware cost are efficiently reduced. According to the experimental results and comparison with existing work, proposed decoder provides a 30% hardware area reduction and a 36% power consumption saving with the same error correcting performance.

本文言語English
ホスト出版物のタイトル2007 International Symposium on Integrated Circuits, ISIC
ページ508-511
ページ数4
DOI
出版ステータスPublished - 2007 12 1
イベント2007 International Symposium on Integrated Circuits, ISIC - Singapore, Singapore
継続期間: 2007 9 262007 9 28

出版物シリーズ

名前2007 International Symposium on Integrated Circuits, ISIC

Conference

Conference2007 International Symposium on Integrated Circuits, ISIC
国/地域Singapore
CitySingapore
Period07/9/2607/9/28

ASJC Scopus subject areas

  • ハードウェアとアーキテクチャ
  • 電子工学および電気工学

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