Cost efficient propagate partial SAD architecture for integer motion estimation in H.264/AVC

Yiqing Huang, Zhenyu Liu, Satoshi Goto, Takeshi Ikenaga

研究成果: Conference contribution

3 被引用数 (Scopus)

抄録

The latest video coding standard H.264/AVC covers a wide range of applications from QCIF to HDTV. In case of HDTV, subsampling technique is widely adopted to reduce hardware cost with little video quality degradation. Moreover, experiments show that contribution of small inter search modes to video quality is trivial so that mode reduction can help to further reduce hardware cost. This paper proposes a cost efficient Propagate Partial SAD architecture for HDTV application. The highly pipelined feature of proposed architecture makes it robust to high speed impact. Compared with widely used SAD Tree structure, the proposed cost efficient structure which adopts subsampling and inter search mode reduction can reduce averagely 23.88% hardware cost with negligible video quality loss. With TSMC 0.18μm CMOS 1P6M standard cell library, the maximum clock speed of this design is 233 MHz in worst work condition (1.62, 125°C).

本文言語English
ホスト出版物のタイトルASICON 2007 - 2007 7th International Conference on ASIC Proceeding
ページ782-785
ページ数4
DOI
出版ステータスPublished - 2007 12 1
イベント2007 7th International Conference on ASIC, ASICON 2007 - Guilin, China
継続期間: 2007 10 262007 10 29

出版物シリーズ

名前ASICON 2007 - 2007 7th International Conference on ASIC Proceeding

Conference

Conference2007 7th International Conference on ASIC, ASICON 2007
国/地域China
CityGuilin
Period07/10/2607/10/29

ASJC Scopus subject areas

  • ハードウェアとアーキテクチャ
  • 電子工学および電気工学

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