Dataflow Optimization through Exploring Single-Layer and Inter-Layer Data Reuse in Memory-Constrained Accelerators

Jinghao Ye, Masao Yanagisawa, Youhua Shi*

*この研究の対応する著者

研究成果: Article査読

抄録

Off-chip memory access has become the performance and energy bottleneck in memory-constrained neural network accelerators. To provide a solution for the energy efficient processing of various neural network models, this paper proposes a dataflow optimization method for modern neural networks by exploring the opportunity of single-layer and inter-layer data reuse to minimize the amount of off-chip memory access in memory-constrained accelerators. A mathematical analysis of three inter-layer data reuse methods is first presented. Then, a comprehensive exploration to determine the optimal data reuse strategy from single-layer and inter-layer data reuse approaches is proposed. The result shows that when compared to the existing single-layer-based exploration method, SmartShuttle, the proposed approach can achieve up to 20.5% and 32.5% of off-chip memory access reduction for ResNeXt-50 and DenseNet-121, respectively.

本文言語English
論文番号2356
ジャーナルElectronics (Switzerland)
11
15
DOI
出版ステータスPublished - 2022 8月

ASJC Scopus subject areas

  • 制御およびシステム工学
  • 信号処理
  • ハードウェアとアーキテクチャ
  • コンピュータ ネットワークおよび通信
  • 電子工学および電気工学

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