DCT/IDCT processor for HDTV developed with dsp silicon compiler

Takashi Miyazaki*, Takao Nishitani, Masato Edahiro, Ikuko Ono, Kaoru Mitsuhashi


研究成果: Article査読

16 被引用数 (Scopus)


This article presents a discrete cosine transform (DCT) processor for high definition television (HDTV) by using an extended version of DSP Silicon Compiler. The extension is mainly concerned with module generation functions. A matrix-vector product module composed of multiply-accumulators (MACs) is newly added to the silicon compiler. The compiler accomplishes placement of leaf-cells and routing between the cells, referring to a prototype layout for the MAC. The prototype, which consists of a Booth multiplier and a carry look ahead adder, is carefully designed to attain high operation speed. The processor developed by the silicon compiler carries out 8×8 DCT and its inverse transform (IDCT). In order to evaluate the newly extended functions in the compiler, the architecture employed for the processor is based on the matrix-vector product method. By using DSP Silicon Compiler and 0.8 μm triple metal CMOS technology, the DCT processor is easily implemented with error-free environment and achieves a 50MHz data rate, which meets Japanese HDTV base line signal processing. The chip is implemented on a 12.80×12.57 mm2 area.

ジャーナルJournal of VLSI Signal Processing
出版ステータスPublished - 1993 4月

ASJC Scopus subject areas

  • 信号処理
  • 情報システム
  • 電子工学および電気工学


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