Deep submicron device isolation with buried insulator between source/drain polysilicon (BIPS)

M. Shimizu*, M. Inuishi, T. Ogawa, H. Miyatake, K. Tsukamoto, Y. Akasaka

*この研究の対応する著者

研究成果: Conference article査読

抄録

A novel isolation technology, called buried insulator between source/drain polysilicon (BIPS), is described. The BIPS isolation structure consists of refilling CVD (chemical vapor deposition) oxides in openings between source/drain polysilicon patterns by double photoresist etchback. A defect- and bird's-beak-free process can be realized by this isolation. Devices with BIPS isolation are compared with LOCOS (local oxidation of silicon) with respect to isolation parasitic effects and current drive capability. A 0.5-μm isolation is achieved, and the narrow channel effects are almost supressed with BIPS isolation. The subthreshold characteristics of devices with BIPS isolation give the same shape value as those for conventional devices with LOCOS isolation. A ring oscillator with BIPS isolation exhibits a propagation delay time of 69 ps/gate.

本文言語English
ページ(範囲)96-99
ページ数4
ジャーナルTechnical Digest - International Electron Devices Meeting
出版ステータスPublished - 1988 12月 1
外部発表はい
イベントTechnical Digest - International Electron Devices Meeting 1988 - San Francisco, CA, USA
継続期間: 1988 12月 111988 12月 14

ASJC Scopus subject areas

  • 電子材料、光学材料、および磁性材料
  • 凝縮系物理学
  • 電子工学および電気工学
  • 材料化学

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