Cryptography plays an important role in the security of data transmission. To ensure the correctness of crypto hardware, we should conduct testing at fabrication and infield. However, the state-of-the-art scan-based test techniques, to achieve high test qualities, need to increase the testability of the circuit under test, which carries a potential of being misused to reveal the secret information of the crypto hardware. Thus, to develop efficient test strategies for crypto hardware to achieve high test quality without compromising security becomes an important task. In this paper we discuss the development of a Design-forSecure-Test (DFST) technique for pipelined AES to overcome the above contradiction between security and test quality in testing crypto hardware. Unlike previous works, the proposed method can keep all the secrets inside and provide high test quality and fault diagnosis ability as well. Furthermore, the proposed DFST technique can significantly reduce test application time, test data volume, and test generation effort as additional benefits.
|ジャーナル||Proceedings - IEEE International Symposium on Circuits and Systems|
|出版物ステータス||Published - 2007 9 27|
|イベント||2007 IEEE International Symposium on Circuits and Systems, ISCAS 2007 - New Orleans, LA, United States|
継続期間: 2007 5 27 → 2007 5 30
ASJC Scopus subject areas
- Electrical and Electronic Engineering