Design-for-secure-test for crypto cores

研究成果: Conference contribution

7 引用 (Scopus)

抜粋

Scan technology carries the potential of being misused as a "side channel" to leak out the secret information of crypto cores. To address such a design challenge, this paper proposes a design-for-secure-test (DFST) solution for crypto cores by adding a stimuli-launched flip-flop into the traditional scan flip-flop to maintain the high test quality without compromising the security.

元の言語English
ホスト出版物のタイトルInternational Test Conference, ITC 2009 - Proceedings
DOI
出版物ステータスPublished - 2009 12 15
イベントInternational Test Conference, ITC 2009 - Austin, TX, United States
継続期間: 2009 11 12009 11 6

出版物シリーズ

名前Proceedings - International Test Conference
ISSN(印刷物)1089-3539

Conference

ConferenceInternational Test Conference, ITC 2009
United States
Austin, TX
期間09/11/109/11/6

ASJC Scopus subject areas

  • Electrical and Electronic Engineering
  • Applied Mathematics

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  • これを引用

    Shi, Y., Togawa, N., Yanagisawa, M., & Ohtsuki, T. (2009). Design-for-secure-test for crypto cores. : International Test Conference, ITC 2009 - Proceedings [5355900] (Proceedings - International Test Conference). https://doi.org/10.1109/TEST.2009.5355900