Design methodology of a robust bsd protection circuit for sti process 256 mb nand flash memory

Tamio Ikehashi, Kenichi Imamiya, Koji Sakui

研究成果: Article

抜粋

With the use of a device simulator, we show that an ESD protection circuit whose junction filled with contacts is suited to a scaled STI process having thin n- junction with n+ being implanted from contact holes. We have confirmed by measurements that the protection has sufficient robustness.

元の言語English
ページ(範囲)246-254
ページ数9
ジャーナルIEEE Transactions on Electronics Packaging Manufacturing
23
発行部数4
DOI
出版物ステータスPublished - 2000 12 1
外部発表Yes

ASJC Scopus subject areas

  • Industrial and Manufacturing Engineering
  • Electrical and Electronic Engineering

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