### 抄録

A TDM/FDM conversion algorithm for realizing transmultiplexers with an FFT processor and a set of digital subfilters is proposed which provides a significant saving in multiplication rate. In the proposed algorithm in which an FDM signal is directly sampled, the dimension of the FFT processor is reduced by provision of pre- and postprocessing and the multiplication rate in radix-3 is reduced by refinement of the processing. The multiplication rate in the subfilters is reduced by the adoption of symmetrical coefficients. Although the direct sampling of an FDM signal has been considered to increase the multiplication rate compared with the sampling with frequency shift of FDM signal, it is estimated that the increase of multiplication rate in the proposed algorithm keeps within 20 percent compared with that in a typical algorithm based on sampling with frequency shift of FDM signal. The proposed algorithm reduces the multiplication rate by 30 percent compared with a previously proposed algorithm based on direct sampling of FDM signal. Based on the proposed algorithm, a digital 60 channel transmuliplexer has been implemented. System configuration of the developed equipment is outlined and its measured performance is described.

元の言語 | English |
---|---|

ページ（範囲） | 1511-1519 |

ページ数 | 9 |

ジャーナル | IEEE Transactions on Communications |

巻 | COM-30 |

発行部数 | 7 pt 1 |

出版物ステータス | Published - 1982 7 |

外部発表 | Yes |

### Fingerprint

### ASJC Scopus subject areas

- Engineering(all)

### これを引用

*IEEE Transactions on Communications*,

*COM-30*(7 pt 1), 1511-1519.

**DIGITAL 60 CHANNEL TRANSMULTIPLEXER : ALGORITHM MINIMIZING MULTIPLICATION RATE AND HARDWARE IMPLEMENTATION.** / Takahata, Fumio; Inagaki, Kazunori; Hirata, Yasuo; Ogawa, Akira.

研究成果: Article

*IEEE Transactions on Communications*, 巻. COM-30, 番号 7 pt 1, pp. 1511-1519.

}

TY - JOUR

T1 - DIGITAL 60 CHANNEL TRANSMULTIPLEXER

T2 - ALGORITHM MINIMIZING MULTIPLICATION RATE AND HARDWARE IMPLEMENTATION.

AU - Takahata, Fumio

AU - Inagaki, Kazunori

AU - Hirata, Yasuo

AU - Ogawa, Akira

PY - 1982/7

Y1 - 1982/7

N2 - A TDM/FDM conversion algorithm for realizing transmultiplexers with an FFT processor and a set of digital subfilters is proposed which provides a significant saving in multiplication rate. In the proposed algorithm in which an FDM signal is directly sampled, the dimension of the FFT processor is reduced by provision of pre- and postprocessing and the multiplication rate in radix-3 is reduced by refinement of the processing. The multiplication rate in the subfilters is reduced by the adoption of symmetrical coefficients. Although the direct sampling of an FDM signal has been considered to increase the multiplication rate compared with the sampling with frequency shift of FDM signal, it is estimated that the increase of multiplication rate in the proposed algorithm keeps within 20 percent compared with that in a typical algorithm based on sampling with frequency shift of FDM signal. The proposed algorithm reduces the multiplication rate by 30 percent compared with a previously proposed algorithm based on direct sampling of FDM signal. Based on the proposed algorithm, a digital 60 channel transmuliplexer has been implemented. System configuration of the developed equipment is outlined and its measured performance is described.

AB - A TDM/FDM conversion algorithm for realizing transmultiplexers with an FFT processor and a set of digital subfilters is proposed which provides a significant saving in multiplication rate. In the proposed algorithm in which an FDM signal is directly sampled, the dimension of the FFT processor is reduced by provision of pre- and postprocessing and the multiplication rate in radix-3 is reduced by refinement of the processing. The multiplication rate in the subfilters is reduced by the adoption of symmetrical coefficients. Although the direct sampling of an FDM signal has been considered to increase the multiplication rate compared with the sampling with frequency shift of FDM signal, it is estimated that the increase of multiplication rate in the proposed algorithm keeps within 20 percent compared with that in a typical algorithm based on sampling with frequency shift of FDM signal. The proposed algorithm reduces the multiplication rate by 30 percent compared with a previously proposed algorithm based on direct sampling of FDM signal. Based on the proposed algorithm, a digital 60 channel transmuliplexer has been implemented. System configuration of the developed equipment is outlined and its measured performance is described.

UR - http://www.scopus.com/inward/record.url?scp=0020153490&partnerID=8YFLogxK

UR - http://www.scopus.com/inward/citedby.url?scp=0020153490&partnerID=8YFLogxK

M3 - Article

AN - SCOPUS:0020153490

VL - COM-30

SP - 1511

EP - 1519

JO - IEEE Transactions on Communications

JF - IEEE Transactions on Communications

SN - 0096-1965

IS - 7 pt 1

ER -