DIGITAL 60 CHANNEL TRANSMULTIPLEXER: ALGORITHM MINIMIZING MULTIPLICATION RATE AND HARDWARE IMPLEMENTATION.

Fumio Takahata, Kazunori Inagaki, Yasuo Hirata, Akira Ogawa

研究成果: Article

4 引用 (Scopus)

抄録

A TDM/FDM conversion algorithm for realizing transmultiplexers with an FFT processor and a set of digital subfilters is proposed which provides a significant saving in multiplication rate. In the proposed algorithm in which an FDM signal is directly sampled, the dimension of the FFT processor is reduced by provision of pre- and postprocessing and the multiplication rate in radix-3 is reduced by refinement of the processing. The multiplication rate in the subfilters is reduced by the adoption of symmetrical coefficients. Although the direct sampling of an FDM signal has been considered to increase the multiplication rate compared with the sampling with frequency shift of FDM signal, it is estimated that the increase of multiplication rate in the proposed algorithm keeps within 20 percent compared with that in a typical algorithm based on sampling with frequency shift of FDM signal. The proposed algorithm reduces the multiplication rate by 30 percent compared with a previously proposed algorithm based on direct sampling of FDM signal. Based on the proposed algorithm, a digital 60 channel transmuliplexer has been implemented. System configuration of the developed equipment is outlined and its measured performance is described.

元の言語English
ページ(範囲)1511-1519
ページ数9
ジャーナルIEEE Transactions on Communications
COM-30
発行部数7 pt 1
出版物ステータスPublished - 1982 7
外部発表Yes

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Frequency division multiplexing
Hardware
Sampling
Fast Fourier transforms
Time division multiplexing
Processing

ASJC Scopus subject areas

  • Engineering(all)

これを引用

DIGITAL 60 CHANNEL TRANSMULTIPLEXER : ALGORITHM MINIMIZING MULTIPLICATION RATE AND HARDWARE IMPLEMENTATION. / Takahata, Fumio; Inagaki, Kazunori; Hirata, Yasuo; Ogawa, Akira.

:: IEEE Transactions on Communications, 巻 COM-30, 番号 7 pt 1, 07.1982, p. 1511-1519.

研究成果: Article

Takahata, Fumio ; Inagaki, Kazunori ; Hirata, Yasuo ; Ogawa, Akira. / DIGITAL 60 CHANNEL TRANSMULTIPLEXER : ALGORITHM MINIMIZING MULTIPLICATION RATE AND HARDWARE IMPLEMENTATION. :: IEEE Transactions on Communications. 1982 ; 巻 COM-30, 番号 7 pt 1. pp. 1511-1519.
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