DIGITAL SPEECH SIGNAL PROCESSOR VLSI: DSSP 1.

Takao Kaneko, Hironori Yamauchi, Atsushi Iwata

研究成果: Article

抜粋

A high-speed programmable digital speech signal processor VLSI (DSSP1) with 18-bit floating-point architecture and 32-bit micro-instructions is developed using 1. 2- mu m CMOS technology. This chip integrates a normalizing floating-point ALU, a 512-w dual-port data RAM, and a 4-Kw micro-program ROM to enable normalizing floating-point operations within a 50-nsec machine-cycle. A high-speed communicative interface that allows a wide variety of configurations to suit various user requirements is provided. The processor VLSI is designed almost entirely with a top-down DA system, which significantly reduces chip size and design time.

元の言語English
ページ(範囲)427-432
ページ数6
ジャーナルReview of the Electrical Communications Laboratories
36
発行部数4
出版物ステータスPublished - 1988 1 1

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ASJC Scopus subject areas

  • Engineering(all)

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