DOUBLE STACKED CAPACITOR WITH SELF-ALIGNED POLY SOURCE/DRAIN TRANSISTOR (DSP) CELL FOR MEGABIT DRAM.

K. Tsukamoto; M. Shimizu; M. Inuishi; Y. Matsuda; H. Oda; H. Morita; M. Nakajima; K. Kobayashi; Y. Mashiko; Y. Akasaka

doi:10.1109/iedm.1987.191423

DOUBLE STACKED CAPACITOR WITH SELF-ALIGNED POLY SOURCE/DRAIN TRANSISTOR (DSP) CELL FOR MEGABIT DRAM.

K. Tsukamoto^*, M. Shimizu, M. Inuishi, Y. Matsuda, H. Oda, H. Morita, M. Nakajima, K. Kobayashi, Y. Mashiko, Y. Akasaka

^*この研究の対応する著者

研究成果: Conference article › 査読

6 被引用数 (Scopus)

抄録

A DRAM cell with a double stacked capacitor and a self-aligned poly source/drain transistor (DSP) cell is described. A storage capacitor is composed of two capacitors stacked in a trench. The first polysilicon acts as a storage node; it is also used as a self-aligned poly source/drain of the access transistor. The isolation region is formed by refilled oxide in openings between the active areas of the first polysilicon. This unique self-aligned structure results in a cell size of 5. 95 mu m**2.

本文言語	English
ページ（範囲）	328-331
ページ数	4
ジャーナル	Technical Digest - International Electron Devices Meeting
DOI	https://doi.org/10.1109/iedm.1987.191423
出版ステータス	Published - 1987
外部発表	はい

ASJC Scopus subject areas

電子材料、光学材料、および磁性材料
凝縮系物理学
材料化学
電子工学および電気工学

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10.1109/iedm.1987.191423

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title = "DOUBLE STACKED CAPACITOR WITH SELF-ALIGNED POLY SOURCE/DRAIN TRANSISTOR (DSP) CELL FOR MEGABIT DRAM.",

abstract = "A DRAM cell with a double stacked capacitor and a self-aligned poly source/drain transistor (DSP) cell is described. A storage capacitor is composed of two capacitors stacked in a trench. The first polysilicon acts as a storage node; it is also used as a self-aligned poly source/drain of the access transistor. The isolation region is formed by refilled oxide in openings between the active areas of the first polysilicon. This unique self-aligned structure results in a cell size of 5. 95 mu m**2.",

author = "K. Tsukamoto and M. Shimizu and M. Inuishi and Y. Matsuda and H. Oda and H. Morita and M. Nakajima and K. Kobayashi and Y. Mashiko and Y. Akasaka",

year = "1987",

doi = "10.1109/iedm.1987.191423",

language = "English",

pages = "328--331",

journal = "Technical Digest - International Electron Devices Meeting",

issn = "0163-1918",

publisher = "Institute of Electrical and Electronics Engineers Inc.",

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TY - JOUR

T1 - DOUBLE STACKED CAPACITOR WITH SELF-ALIGNED POLY SOURCE/DRAIN TRANSISTOR (DSP) CELL FOR MEGABIT DRAM.

AU - Tsukamoto, K.

AU - Shimizu, M.

AU - Inuishi, M.

AU - Matsuda, Y.

AU - Oda, H.

AU - Morita, H.

AU - Nakajima, M.

AU - Kobayashi, K.

AU - Mashiko, Y.

AU - Akasaka, Y.

PY - 1987

Y1 - 1987

N2 - A DRAM cell with a double stacked capacitor and a self-aligned poly source/drain transistor (DSP) cell is described. A storage capacitor is composed of two capacitors stacked in a trench. The first polysilicon acts as a storage node; it is also used as a self-aligned poly source/drain of the access transistor. The isolation region is formed by refilled oxide in openings between the active areas of the first polysilicon. This unique self-aligned structure results in a cell size of 5. 95 mu m**2.

AB - A DRAM cell with a double stacked capacitor and a self-aligned poly source/drain transistor (DSP) cell is described. A storage capacitor is composed of two capacitors stacked in a trench. The first polysilicon acts as a storage node; it is also used as a self-aligned poly source/drain of the access transistor. The isolation region is formed by refilled oxide in openings between the active areas of the first polysilicon. This unique self-aligned structure results in a cell size of 5. 95 mu m**2.

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U2 - 10.1109/iedm.1987.191423

DO - 10.1109/iedm.1987.191423

M3 - Conference article

AN - SCOPUS:0023541357

SP - 328

EP - 331

JO - Technical Digest - International Electron Devices Meeting

JF - Technical Digest - International Electron Devices Meeting

SN - 0163-1918

ER -

DOUBLE STACKED CAPACITOR WITH SELF-ALIGNED POLY SOURCE/DRAIN TRANSISTOR (DSP) CELL FOR MEGABIT DRAM.

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