A DRAM cell with a double stacked capacitor and a self-aligned poly source/drain transistor (DSP) cell is described. A storage capacitor is composed of two capacitors stacked in a trench. The first polysilicon acts as a storage node; it is also used as a self-aligned poly source/drain of the access transistor. The isolation region is formed by refilled oxide in openings between the active areas of the first polysilicon. This unique self-aligned structure results in a cell size of 5. 95 mu m**2.
|ジャーナル||Technical Digest - International Electron Devices Meeting|
|出版ステータス||Published - 1987|
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