抄録
A DRAM cell with a double stacked capacitor and a self-aligned poly source/drain transistor (DSP) cell is described. A storage capacitor is composed of two capacitors stacked in a trench. The first polysilicon acts as a storage node; it is also used as a self-aligned poly source/drain of the access transistor. The isolation region is formed by refilled oxide in openings between the active areas of the first polysilicon. This unique self-aligned structure results in a cell size of 5. 95 mu m**2.
本文言語 | English |
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ページ(範囲) | 328-331 |
ページ数 | 4 |
ジャーナル | Technical Digest - International Electron Devices Meeting |
DOI | |
出版ステータス | Published - 1987 |
外部発表 | はい |
ASJC Scopus subject areas
- 電子材料、光学材料、および磁性材料
- 凝縮系物理学
- 材料化学
- 電子工学および電気工学