DOUBLE STACKED CAPACITOR WITH SELF-ALIGNED POLY SOURCE/DRAIN TRANSISTOR (DSP) CELL FOR MEGABIT DRAM.

K. Tsukamoto, M. Shimizu, M. Inuishi, Y. Matsuda, H. Oda, H. Morita, M. Nakajima, K. Kobayashi, Y. Mashiko, Y. Akasaka

研究成果: Conference article査読

5 被引用数 (Scopus)

抄録

A DRAM cell with a double stacked capacitor and a self-aligned poly source/drain transistor (DSP) cell is described. A storage capacitor is composed of two capacitors stacked in a trench. The first polysilicon acts as a storage node; it is also used as a self-aligned poly source/drain of the access transistor. The isolation region is formed by refilled oxide in openings between the active areas of the first polysilicon. This unique self-aligned structure results in a cell size of 5. 95 mu m**2.

本文言語English
ページ(範囲)328-331
ページ数4
ジャーナルTechnical Digest - International Electron Devices Meeting
出版ステータスPublished - 1987 12 1
外部発表はい

ASJC Scopus subject areas

  • Electronic, Optical and Magnetic Materials
  • Condensed Matter Physics
  • Electrical and Electronic Engineering
  • Materials Chemistry

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