Dummy filling methods for reducing interconnect capacitance and number of fills

Atsushi Kurokawa, Toshiki Kanamoto, Tetsuya Ibe, Akira Kasebe, Chang Wei Fong, Tetsuro Kage, Yasuaki Inoue, Hiroo Masuda

    研究成果: Conference contribution

    29 被引用数 (Scopus)

    抄録

    In recent system-on-chip (SoC) designs, floating dummy metals inserted for planarization have created serious problems because of increased interconnect capacitance and the enormous amount of fill required. We present new methods to reduce the interconnect capacitance and the amount of dummy metals needed. These techniques include three ways of filling: (1) improved floating square fills, (2) floating parallel lines, and (3) floating perpendicular lines (with spacing between dummy metals above and below signal lines). We also present efficient simple formulas for estimating the appropriate spacing and number of fills. In our experiments, the capacitance increase using the traditional regular square method was 13.1%, while that using the methods of improved square fills, extended parallel lines, and perpendicular lines was 2.5%, 2.4%, and 1.1%, respectively. Moreover, the number of necessary dummy metals can be reduced by two orders of magnitude through use of the parallel line method.

    本文言語English
    ホスト出版物のタイトルProceedings - International Symposium on Quality Electronic Design, ISQED
    ページ586-591
    ページ数6
    DOI
    出版ステータスPublished - 2005
    イベント6th International Symposium on Quality Electronic Design, ISQED 2005 - San Jose, CA
    継続期間: 2005 3 212005 3 23

    Other

    Other6th International Symposium on Quality Electronic Design, ISQED 2005
    CitySan Jose, CA
    Period05/3/2105/3/23

    ASJC Scopus subject areas

    • ハードウェアとアーキテクチャ
    • 電子工学および電気工学
    • 安全性、リスク、信頼性、品質管理

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