抄録
The authors propose an analytic method of predicting pattern edge enhanced leakage currents in MOS capacitors with arbitrary geometry, based on test chip I-V measurements. The predicted results are in good agreement with experimental results. Using this method, it becomes possible to qualitatively compare the magnitudes of edge effects under different processing conditions. It is concluded that this method will be a powerful tool for developing high-reliability insulators in future LSIs.
| 本文言語 | English |
|---|---|
| ホスト出版物のタイトル | Test Structures |
| Place of Publication | Piscataway, NJ, United States |
| 出版社 | Publ by IEEE |
| ページ | 17-22 |
| ページ数 | 6 |
| ISBN（印刷版） | 0879425881 |
| 出版ステータス | Published - 1991 |
| イベント | Proceedings of the 1991 International Conference on Microelectronic Test Structures - Kyoto, Jpn 継続期間: 1991 3月 18 → 1991 3月 20 |
Other
| Other | Proceedings of the 1991 International Conference on Microelectronic Test Structures |
|---|---|
| City | Kyoto, Jpn |
| Period | 91/3/18 → 91/3/20 |
ASJC Scopus subject areas
- 工学（全般）