Edge effect prediction in real MOS insulator using test chips

Jiro Yugami*, Atsushi Hiraiwa

*この研究の対応する著者

研究成果

3 被引用数 (Scopus)

抄録

The authors propose an analytic method of predicting pattern edge enhanced leakage currents in MOS capacitors with arbitrary geometry, based on test chip I-V measurements. The predicted results are in good agreement with experimental results. Using this method, it becomes possible to qualitatively compare the magnitudes of edge effects under different processing conditions. It is concluded that this method will be a powerful tool for developing high-reliability insulators in future LSIs.

本文言語English
ホスト出版物のタイトルTest Structures
Place of PublicationPiscataway, NJ, United States
出版社Publ by IEEE
ページ17-22
ページ数6
ISBN(印刷版)0879425881
出版ステータスPublished - 1991
イベントProceedings of the 1991 International Conference on Microelectronic Test Structures - Kyoto, Jpn
継続期間: 1991 3 181991 3 20

Other

OtherProceedings of the 1991 International Conference on Microelectronic Test Structures
CityKyoto, Jpn
Period91/3/1891/3/20

ASJC Scopus subject areas

  • 工学(全般)

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