抜粋
The authors propose an analytic method of predicting pattern edge enhanced leakage currents in MOS capacitors with arbitrary geometry, based on test chip I-V measurements. The predicted results are in good agreement with experimental results. Using this method, it becomes possible to qualitatively compare the magnitudes of edge effects under different processing conditions. It is concluded that this method will be a powerful tool for developing high-reliability insulators in future LSIs.
| 元の言語 | English |
|---|---|
| ホスト出版物のタイトル | Test Structures |
| 出版場所 | Piscataway, NJ, United States |
| 出版者 | Publ by IEEE |
| ページ | 17-22 |
| ページ数 | 6 |
| ISBN（印刷物） | 0879425881 |
| 出版物ステータス | Published - 1991 |
| イベント | Proceedings of the 1991 International Conference on Microelectronic Test Structures - Kyoto, Jpn 継続期間: 1991 3 18 → 1991 3 20 |
Other
| Other | Proceedings of the 1991 International Conference on Microelectronic Test Structures |
|---|---|
| 市 | Kyoto, Jpn |
| 期間 | 91/3/18 → 91/3/20 |
フィンガープリント
ASJC Scopus subject areas
- Engineering(all)
これを引用
Yugami, J., & Hiraiwa, A. (1991). Edge effect prediction in real MOS insulator using test chips. ： Test Structures (pp. 17-22). Publ by IEEE.