EFFECT OF PRE-ANNEALING IN PREVENTING GATE OXIDE BREAKDOWN VOLTAGE DEGRADATION INDUCED BY POLYSILICON GATE DELINEATION USING ION MILLING.

Noriyoshi Yamauchi, Toshiaki Yachi, Tsutomu Wada

研究成果: Article査読

抄録

Ion milling is one of the promising methods for submicron pattern delineation in VLSI processes because of its potential for extremely small undercutting and high control. In gate electrode delineation using dry etching, degradation of the gate oxide must be avoided. The purpose of this work is to find those ion milling conditions where the gate oxide breakdown voltage is not degraded. Polysilicon gate MOS capacitors were fabricated delineating polysilicon films of various resistance by ion milling, and the breakdown voltage for the MOS capacitors was measured. The degradation was prevented when the polysilicon sheet resistance was lowered by annealing before ion milling.

本文言語English
ページ(範囲)539-540
ページ数2
ジャーナルJapanese Journal of Applied Physics, Part 2: Letters
22
8
DOI
出版ステータスPublished - 1983

ASJC Scopus subject areas

  • Engineering(all)
  • Physics and Astronomy (miscellaneous)
  • Physics and Astronomy(all)

フィンガープリント 「EFFECT OF PRE-ANNEALING IN PREVENTING GATE OXIDE BREAKDOWN VOLTAGE DEGRADATION INDUCED BY POLYSILICON GATE DELINEATION USING ION MILLING.」の研究トピックを掘り下げます。これらがまとまってユニークなフィンガープリントを構成します。

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