Effective capacitance for gate delay with RC loads

Zhang Cai Huang, Atsushi Kurokawa, Yasuaki Inoue

    研究成果: Conference contribution

    6 引用 (Scopus)

    抄録

    In deep submicron designs, the resistance of interconnect is playing dominant role on the timing behavior of logic gates. The concept of effective capacitance C eff is usually used to calculate the gate delay for interconnect loads. In this paper, a new method to derive the expression C eff is presented, and the accuracy of the expression is discussed. In our approach, the output waveform is assumed as linear. Thus, the expression of effective capacitance is simple and efficient. Moreover, the result of effective capacitance is insensitive to output wave shape because C eff is determined by the curve area. Therefore, it is appropriate for various output waveform of CMOS gate with RC loads. Experimental results show it is in agreement with the Spice simulation.

    元の言語English
    ホスト出版物のタイトルProceedings - IEEE International Symposium on Circuits and Systems
    ページ2795-2798
    ページ数4
    DOI
    出版物ステータスPublished - 2005
    イベントIEEE International Symposium on Circuits and Systems 2005, ISCAS 2005 - Kobe, Japan
    継続期間: 2005 5 232005 5 26

    Other

    OtherIEEE International Symposium on Circuits and Systems 2005, ISCAS 2005
    Japan
    Kobe
    期間05/5/2305/5/26

    Fingerprint

    Capacitance
    Logic gates

    ASJC Scopus subject areas

    • Electrical and Electronic Engineering

    これを引用

    Huang, Z. C., Kurokawa, A., & Inoue, Y. (2005). Effective capacitance for gate delay with RC loads. : Proceedings - IEEE International Symposium on Circuits and Systems (pp. 2795-2798). [1465207] https://doi.org/10.1109/ISCAS.2005.1465207

    Effective capacitance for gate delay with RC loads. / Huang, Zhang Cai; Kurokawa, Atsushi; Inoue, Yasuaki.

    Proceedings - IEEE International Symposium on Circuits and Systems. 2005. p. 2795-2798 1465207.

    研究成果: Conference contribution

    Huang, ZC, Kurokawa, A & Inoue, Y 2005, Effective capacitance for gate delay with RC loads. : Proceedings - IEEE International Symposium on Circuits and Systems., 1465207, pp. 2795-2798, IEEE International Symposium on Circuits and Systems 2005, ISCAS 2005, Kobe, Japan, 05/5/23. https://doi.org/10.1109/ISCAS.2005.1465207
    Huang ZC, Kurokawa A, Inoue Y. Effective capacitance for gate delay with RC loads. : Proceedings - IEEE International Symposium on Circuits and Systems. 2005. p. 2795-2798. 1465207 https://doi.org/10.1109/ISCAS.2005.1465207
    Huang, Zhang Cai ; Kurokawa, Atsushi ; Inoue, Yasuaki. / Effective capacitance for gate delay with RC loads. Proceedings - IEEE International Symposium on Circuits and Systems. 2005. pp. 2795-2798
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    abstract = "In deep submicron designs, the resistance of interconnect is playing dominant role on the timing behavior of logic gates. The concept of effective capacitance C eff is usually used to calculate the gate delay for interconnect loads. In this paper, a new method to derive the expression C eff is presented, and the accuracy of the expression is discussed. In our approach, the output waveform is assumed as linear. Thus, the expression of effective capacitance is simple and efficient. Moreover, the result of effective capacitance is insensitive to output wave shape because C eff is determined by the curve area. Therefore, it is appropriate for various output waveform of CMOS gate with RC loads. Experimental results show it is in agreement with the Spice simulation.",
    author = "Huang, {Zhang Cai} and Atsushi Kurokawa and Yasuaki Inoue",
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    AU - Inoue, Yasuaki

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    AB - In deep submicron designs, the resistance of interconnect is playing dominant role on the timing behavior of logic gates. The concept of effective capacitance C eff is usually used to calculate the gate delay for interconnect loads. In this paper, a new method to derive the expression C eff is presented, and the accuracy of the expression is discussed. In our approach, the output waveform is assumed as linear. Thus, the expression of effective capacitance is simple and efficient. Moreover, the result of effective capacitance is insensitive to output wave shape because C eff is determined by the curve area. Therefore, it is appropriate for various output waveform of CMOS gate with RC loads. Experimental results show it is in agreement with the Spice simulation.

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