Effective write-reduction method for MLC non-volatile memory

研究成果: Conference contribution

抜粋

Recently, the requirement for non-volatile memory on embedded systems has increased because they can be applied with normally-off and power gating technologies to. However, they have a lower endurance than volatile memories. When data is encoded as a write-reduction code appropriately, the endurance of non-volatile memory can be enhanced by writing the encoded data into the memory. We propose a highly effective write-reduction method for a multi-level cell (MLC) non-volatile memory focusing on the write-reduction code (WRC) as the optimal bit-write reduction method. The WRC can be applied only to single-level cell non-volatile memory. The proposed method generates a cell-write reduction code based on the WRC; the cell has multiple bits as the holdable data. Our proposed method achieves a cell-write reduction by 31.6% compared to the conventional method.

元の言語English
ホスト出版物のタイトルIEEE International Symposium on Circuits and Systems
ホスト出版物のサブタイトルFrom Dreams to Innovation, ISCAS 2017 - Conference Proceedings
出版者Institute of Electrical and Electronics Engineers Inc.
ISBN(電子版)9781467368520
DOI
出版物ステータスPublished - 2017 9 25
イベント50th IEEE International Symposium on Circuits and Systems, ISCAS 2017 - Baltimore, United States
継続期間: 2017 5 282017 5 31

Other

Other50th IEEE International Symposium on Circuits and Systems, ISCAS 2017
United States
Baltimore
期間17/5/2817/5/31

ASJC Scopus subject areas

  • Electrical and Electronic Engineering

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  • これを引用

    Tawada, M., Kimura, S., Yanagisawa, M., & Togawa, N. (2017). Effective write-reduction method for MLC non-volatile memory. : IEEE International Symposium on Circuits and Systems: From Dreams to Innovation, ISCAS 2017 - Conference Proceedings [8050699] Institute of Electrical and Electronics Engineers Inc.. https://doi.org/10.1109/ISCAS.2017.8050699