Effectively Partitioned Implementation for Successive-Cancellation Polar Decoder

Yuta Ideguchi, Norifumi Kamiya, Masashi Tawada, Nozomu Togawa

研究成果: Conference contribution

抜粋

This paper proposes an effective field-programmable gate array (FPGA) implementation of a successive-cancellation (SC) decoder for polar codes that have recently attracted attention as error-correcting codes adopted for 5G wireless systems. We focus on effective ways of partitioning the SC decoding procedure into combinational and sequential logic parts. It can be shown that the SC decoder of length N(= N1N2) can be divided into two parts: N1 SC decoders of length N2 and a single SC decoder of length N1. While the N1 decoders in the first part can perform in parallel, the decoding procedure in the second part is performed sequentially, which causes a bottleneck due to a long latency. We present an SC decoder architecture in which the first part is implemented using sequential logic circuits, and the second part is implemented using only combinational logic circuits. The overall latency and clock frequency of the decoder are balanced by the divisor N1 of N, and we show that an appropriate choice of N1 yields an efficient implementation with a high throughput. We demonstrate an FPGA implementation of the decoder architecture for a 1024-bit-length polar code and show that our FPGA decoder can achieve three times higher throughput than the conventional sequential semi-parallel decoder without significantly increasing the hardware resources.

元の言語English
ホスト出版物のタイトル2019 IEEE 62nd International Midwest Symposium on Circuits and Systems, MWSCAS 2019
出版者Institute of Electrical and Electronics Engineers Inc.
ページ981-984
ページ数4
ISBN(電子版)9781728127880
DOI
出版物ステータスPublished - 2019 8
イベント62nd IEEE International Midwest Symposium on Circuits and Systems, MWSCAS 2019 - Dallas, United States
継続期間: 2019 8 42019 8 7

出版物シリーズ

名前Midwest Symposium on Circuits and Systems
2019-August
ISSN(印刷物)1548-3746

Conference

Conference62nd IEEE International Midwest Symposium on Circuits and Systems, MWSCAS 2019
United States
Dallas
期間19/8/419/8/7

ASJC Scopus subject areas

  • Electronic, Optical and Magnetic Materials
  • Electrical and Electronic Engineering

フィンガープリント Effectively Partitioned Implementation for Successive-Cancellation Polar Decoder' の研究トピックを掘り下げます。これらはともに一意のフィンガープリントを構成します。

  • これを引用

    Ideguchi, Y., Kamiya, N., Tawada, M., & Togawa, N. (2019). Effectively Partitioned Implementation for Successive-Cancellation Polar Decoder. : 2019 IEEE 62nd International Midwest Symposium on Circuits and Systems, MWSCAS 2019 (pp. 981-984). [8885174] (Midwest Symposium on Circuits and Systems; 巻数 2019-August). Institute of Electrical and Electronics Engineers Inc.. https://doi.org/10.1109/MWSCAS.2019.8885174