Efficient dummy filling methods to reduce interconnect capacitance and number of dummy metal fills

Atsushi Kurokawa*, Toshiki Kanamoto, Tetsuya Ibe, Akira Kasebe, Wei Fong Chang, Tetsuro Kage, Yasuaki Inoue, Hiroo Masuda

*この研究の対応する著者

    研究成果: Article査読

    3 被引用数 (Scopus)

    抄録

    Floating dummy metal fills inserted for planarization of multi-dielectric layers have created serious problems because of increased interconnect capacitance and the enormous number of fills. We present new dummy filling methods to reduce the interconnect capacitance and the number of dummy metal fills needed. These techniques include three ways of filling: 1) improved floating square fills, 2) floating parallel lines, and 3) floating perpendicular lines (with spacing between dummy metal fills above and below signal lines). We also present efficient formulas for estimating the appropriate spacing and number of fills. In our experiments, the capacitance increase using the conventional regular square method was 13.1%, while that using the methods of improved square fills, extended parallel lines, and perpendicular lines were 2.7%, 2.4%, and 1.0%, respectively. Moreover, the number of necessary dummy metal fills can be reduced by two orders of magnitude through use of the parallel line method.

    本文言語English
    ページ(範囲)3471-3477
    ページ数7
    ジャーナルIEICE Transactions on Fundamentals of Electronics, Communications and Computer Sciences
    E88-A
    12
    DOI
    出版ステータスPublished - 2005 12

    ASJC Scopus subject areas

    • 電子工学および電気工学
    • ハードウェアとアーキテクチャ
    • 情報システム

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