### 抄録

The optimum placement of blocks on a two-dimensional chip, which minimizes the total routing length of signal nets is considered. A new heuristic procedure, based on iterative improvement, is proposed. The procedure repeats random generation of an initial solution and its improvement by a sequence of local transformations. The best among the local optimum solutions is taken as a final solution. The iterative improvement method proposed here is different from the previous one, in the sense that it considers interchanging more than two blocks at the same time and examines only a small portion of feasible solutions which has high probability of being better. Experimental results show this procedure gives better solutions than the best one up to now. The computation time for each local optimum solution grows almost linearly with regard to the number of blocks.

元の言語 | English |
---|---|

ページ（範囲） | 24-32 |

ページ数 | 9 |

ジャーナル | NEC Research and Development |

発行部数 | 65 |

出版物ステータス | Published - 1982 4 |

### ASJC Scopus subject areas

- Electrical and Electronic Engineering

### これを引用

*NEC Research and Development*, (65), 24-32.

**EFFICIENT TWO-DIMENSIONAL PLACEMENT ALGORITHM FOR THE MASTER-SLICE LSI LAYOUT.** / Goto, Satoshi.

研究成果: Article

*NEC Research and Development*, 番号 65, pp. 24-32.

}

TY - JOUR

T1 - EFFICIENT TWO-DIMENSIONAL PLACEMENT ALGORITHM FOR THE MASTER-SLICE LSI LAYOUT.

AU - Goto, Satoshi

PY - 1982/4

Y1 - 1982/4

N2 - The optimum placement of blocks on a two-dimensional chip, which minimizes the total routing length of signal nets is considered. A new heuristic procedure, based on iterative improvement, is proposed. The procedure repeats random generation of an initial solution and its improvement by a sequence of local transformations. The best among the local optimum solutions is taken as a final solution. The iterative improvement method proposed here is different from the previous one, in the sense that it considers interchanging more than two blocks at the same time and examines only a small portion of feasible solutions which has high probability of being better. Experimental results show this procedure gives better solutions than the best one up to now. The computation time for each local optimum solution grows almost linearly with regard to the number of blocks.

AB - The optimum placement of blocks on a two-dimensional chip, which minimizes the total routing length of signal nets is considered. A new heuristic procedure, based on iterative improvement, is proposed. The procedure repeats random generation of an initial solution and its improvement by a sequence of local transformations. The best among the local optimum solutions is taken as a final solution. The iterative improvement method proposed here is different from the previous one, in the sense that it considers interchanging more than two blocks at the same time and examines only a small portion of feasible solutions which has high probability of being better. Experimental results show this procedure gives better solutions than the best one up to now. The computation time for each local optimum solution grows almost linearly with regard to the number of blocks.

UR - http://www.scopus.com/inward/record.url?scp=0020120579&partnerID=8YFLogxK

UR - http://www.scopus.com/inward/citedby.url?scp=0020120579&partnerID=8YFLogxK

M3 - Article

AN - SCOPUS:0020120579

SP - 24

EP - 32

JO - NEC Research and Development

JF - NEC Research and Development

SN - 0048-0436

IS - 65

ER -