EFFICIENT TWO-DIMENSIONAL PLACEMENT ALGORITHM FOR THE MASTER-SLICE LSI LAYOUT.

Satoshi Goto

    研究成果: Article

    抄録

    The optimum placement of blocks on a two-dimensional chip, which minimizes the total routing length of signal nets is considered. A new heuristic procedure, based on iterative improvement, is proposed. The procedure repeats random generation of an initial solution and its improvement by a sequence of local transformations. The best among the local optimum solutions is taken as a final solution. The iterative improvement method proposed here is different from the previous one, in the sense that it considers interchanging more than two blocks at the same time and examines only a small portion of feasible solutions which has high probability of being better. Experimental results show this procedure gives better solutions than the best one up to now. The computation time for each local optimum solution grows almost linearly with regard to the number of blocks.

    元の言語English
    ページ(範囲)24-32
    ページ数9
    ジャーナルNEC Research and Development
    発行部数65
    出版物ステータスPublished - 1982 4

    ASJC Scopus subject areas

    • Electrical and Electronic Engineering

    これを引用

    EFFICIENT TWO-DIMENSIONAL PLACEMENT ALGORITHM FOR THE MASTER-SLICE LSI LAYOUT. / Goto, Satoshi.

    :: NEC Research and Development, 番号 65, 04.1982, p. 24-32.

    研究成果: Article

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