We measured the electrical properties of vertically aligned carbon nanotubes (CNTs) synthesized from via holes by radical chemical vapor deposition at a low temperature of 390°C, which meets the requirements of the Si large scale integration (LSI) process. To use the CNTs could be used for LSI wiring, we applied chemical mechanical polishing (CMP) to the CNTs and successfully reduced the via resistance by a factor often. In addition, the resistance of the CNTs was reduced further to 0.6 Ω for 2-μm-diameter vias by annealing at 400°C. Although the temperature dependence of the resistance of the CNTs grown in vias (CNT-vias) did not indicate ballistic transport, which is one of the expected properties of CNTs, we found that CMP and annealing are effective for reducing the via resistance of CNTs.
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