EM-X parallel computer: Architecture and basic performance

Yuetsu Kodama, Hirohumi Sakane, Mitsuhisa Sato, Hayato Yamana, Shuichi Sakai, Yoshinori Yamaguchi

研究成果: Conference contribution

9 被引用数 (Scopus)

抄録

Latency tolerance is essential in achieving high performance on parallel computers for remote function calls and fine-grained remote memory accesses. EM-X supports interprocessor communication on an execution pipeline with small and simple packets. It can create a packet in one cycle, and receive a packet from the network in the on-chip buffer without interruption. EM-X invokes threads on packet arrival, minimizing the overhead of thread switching. It can tolerate communication latency by using efficient multi-threading and optimizing packet flow of fine grain communication. EM-X also supports the synchronization of two operands, direct remote memory read/write operations and flexible packet scheduling with priority. This paper describes distinctive features of the EM-X architecture and reports the performance of small synthetic programs and larger more realistic programs.

本文言語English
ホスト出版物のタイトルConference Proceedings - Annual International Symposium on Computer Architecture, ISCA
ページ14-23
ページ数10
出版ステータスPublished - 1995 1 1
外部発表はい
イベントProceedings of the 1995 22nd Annual International Symposium on Computer Architecture - Santa Margherita Ligure, Italy
継続期間: 1995 6 221995 6 24

出版物シリーズ

名前Conference Proceedings - Annual International Symposium on Computer Architecture, ISCA
ISSN(印刷版)0884-7495

Other

OtherProceedings of the 1995 22nd Annual International Symposium on Computer Architecture
CitySanta Margherita Ligure, Italy
Period95/6/2295/6/24

ASJC Scopus subject areas

  • ハードウェアとアーキテクチャ

フィンガープリント

「EM-X parallel computer: Architecture and basic performance」の研究トピックを掘り下げます。これらがまとまってユニークなフィンガープリントを構成します。

引用スタイル