Embedded low-power dynamic TCAM architecture with transparently scheduled refresh

Hideyuki Noda*, Kazunari Inoue, Hans Jürgen Mattausch, Tetsushi Koide, Katsumi Dosaka, Kazutami Arimoto, Kazuyasu Fujishima, Kenji Anami, Tsutomu Yoshihara

*この研究の対応する著者

    研究成果: Article査読

    1 被引用数 (Scopus)

    抄録

    This paper describes a dynamic TCAM architecture with planar complementary capacitors, transparently scheduled refresh (TSR), autonomous power management (APM) and address-input-free writing scheme. The complementary cell structure of the planar dynamic TCAM (PD-TCAM) allows small cell size of 4.79 μm 2 in 130 nm CMOS technology, and realizes stable TCAM operation even with very small storage capacitance. Due to the TSR architecture, the PD-TCAM maintains functional compatibility with a conventional SRAM-based TCAM. The combined effects of the compact PD-TCAM array matrix and the APM technique result in up to 50% reduction of the total power consumption during search operation. In addition, an intelligent address-input-free writing scheme is also introduced to facilitate the PD-TCAM application for the user. Consequently the proposed architecture is quite attractive for realizing compact and low-power embedded TCAM macros for the design of system VLSI solutions in the field of networking applications.

    本文言語English
    ページ(範囲)622-629
    ページ数8
    ジャーナルIEICE Transactions on Electronics
    E88-C
    4
    DOI
    出版ステータスPublished - 2005 4月

    ASJC Scopus subject areas

    • 電子工学および電気工学

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