Energy-Efficient and High Performance Approximate Multiplier Using Compressors Based on Input Reordering

Zhenhao Liu, Yi Guo, Xiaoting Sun, Shinji Kimura

研究成果

抄録

Today in nanometer regime, approximate circuits have attracted much more attention due to the pursuit of low power consumption and high performance. Approximate multiplier is the key arithmetic function in many error-tolerant applications such as signal processing. In this paper, two approximate compressors based on input reordering logic have been proposed for the partial product reduction in the multiplication. A 2-bit reordering circuit is also designed for the proposed multiplier. Experimental results show that the proposed multiplier sacrifices only a small amount of precision (about 0.58%) to drastically reduce power, area, and delay up to (36.6%), (28.8%) and (20.1%) compared to accurate Wallace multiplier. The proposed multiplier achieves a high signal-to-noise ratio (over 50dB) when applied to an image processing algorithm.

本文言語English
ホスト出版物のタイトルProceedings of TENCON 2018 - 2018 IEEE Region 10 Conference
出版社Institute of Electrical and Electronics Engineers Inc.
ページ545-550
ページ数6
ISBN(電子版)9781538654576
DOI
出版ステータスPublished - 2019 2 22
イベント2018 IEEE Region 10 Conference, TENCON 2018 - Jeju, Korea, Republic of
継続期間: 2018 10 282018 10 31

出版物シリーズ

名前IEEE Region 10 Annual International Conference, Proceedings/TENCON
2018-October
ISSN(印刷版)2159-3442
ISSN(電子版)2159-3450

Conference

Conference2018 IEEE Region 10 Conference, TENCON 2018
国/地域Korea, Republic of
CityJeju
Period18/10/2818/10/31

ASJC Scopus subject areas

  • コンピュータ サイエンスの応用
  • 電子工学および電気工学

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