Energy-efficient high-level synthesis for HDR architecture with multi-stage clock gating

Hiroyuki Akasaka, Shin Ya Abe, Masao Yanagisawa, Nozomu Togawa

    研究成果: Article

    抄録

    With the miniaturization and high performance of current and future LSIs, demand for portable devices has much more increased. Especially the problems of battery runtime and device overheating have occurred. In addition, with the downsize of the LSI design process, the ratio of an interconnection delay to a gate delay has continued to increase. High-level synthesis to estimate the interconnection delays and reduce energy consumption is essential. In this paper, we propose a high-level synthesis algorithm based on HDR architectures (huddle-based distributed register architectures) utilizing multi-stage clock gating. By increasing the number of clock gating stages in each huddle, we increase the number of the control steps at which we can apply the clock gating to registers. We can determine the configuration of the clock gating with optimized energy consumption. The experimental results demonstrate that our proposed algorithm reduced energy consumption by up to 27.7% compared with conventional algorithms.

    元の言語English
    ページ(範囲)74-80
    ページ数7
    ジャーナルIPSJ Transactions on System LSI Design Methodology
    7
    DOI
    出版物ステータスPublished - 2014

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    Clocks
    Energy utilization
    High level synthesis

    ASJC Scopus subject areas

    • Electrical and Electronic Engineering
    • Computer Science Applications

    これを引用

    @article{e846dedcc9dd469bb20855073b983266,
    title = "Energy-efficient high-level synthesis for HDR architecture with multi-stage clock gating",
    abstract = "With the miniaturization and high performance of current and future LSIs, demand for portable devices has much more increased. Especially the problems of battery runtime and device overheating have occurred. In addition, with the downsize of the LSI design process, the ratio of an interconnection delay to a gate delay has continued to increase. High-level synthesis to estimate the interconnection delays and reduce energy consumption is essential. In this paper, we propose a high-level synthesis algorithm based on HDR architectures (huddle-based distributed register architectures) utilizing multi-stage clock gating. By increasing the number of clock gating stages in each huddle, we increase the number of the control steps at which we can apply the clock gating to registers. We can determine the configuration of the clock gating with optimized energy consumption. The experimental results demonstrate that our proposed algorithm reduced energy consumption by up to 27.7{\%} compared with conventional algorithms.",
    keywords = "Clock gating timing, Gating step count, High-level synthesis, Huddle-based distributed register architecture, Multi-stage clock gating",
    author = "Hiroyuki Akasaka and Abe, {Shin Ya} and Masao Yanagisawa and Nozomu Togawa",
    year = "2014",
    doi = "10.2197/ipsjtsldm.7.74",
    language = "English",
    volume = "7",
    pages = "74--80",
    journal = "IPSJ Transactions on System LSI Design Methodology",
    issn = "1882-6687",
    publisher = "Information Processing Society of Japan",

    }

    TY - JOUR

    T1 - Energy-efficient high-level synthesis for HDR architecture with multi-stage clock gating

    AU - Akasaka, Hiroyuki

    AU - Abe, Shin Ya

    AU - Yanagisawa, Masao

    AU - Togawa, Nozomu

    PY - 2014

    Y1 - 2014

    N2 - With the miniaturization and high performance of current and future LSIs, demand for portable devices has much more increased. Especially the problems of battery runtime and device overheating have occurred. In addition, with the downsize of the LSI design process, the ratio of an interconnection delay to a gate delay has continued to increase. High-level synthesis to estimate the interconnection delays and reduce energy consumption is essential. In this paper, we propose a high-level synthesis algorithm based on HDR architectures (huddle-based distributed register architectures) utilizing multi-stage clock gating. By increasing the number of clock gating stages in each huddle, we increase the number of the control steps at which we can apply the clock gating to registers. We can determine the configuration of the clock gating with optimized energy consumption. The experimental results demonstrate that our proposed algorithm reduced energy consumption by up to 27.7% compared with conventional algorithms.

    AB - With the miniaturization and high performance of current and future LSIs, demand for portable devices has much more increased. Especially the problems of battery runtime and device overheating have occurred. In addition, with the downsize of the LSI design process, the ratio of an interconnection delay to a gate delay has continued to increase. High-level synthesis to estimate the interconnection delays and reduce energy consumption is essential. In this paper, we propose a high-level synthesis algorithm based on HDR architectures (huddle-based distributed register architectures) utilizing multi-stage clock gating. By increasing the number of clock gating stages in each huddle, we increase the number of the control steps at which we can apply the clock gating to registers. We can determine the configuration of the clock gating with optimized energy consumption. The experimental results demonstrate that our proposed algorithm reduced energy consumption by up to 27.7% compared with conventional algorithms.

    KW - Clock gating timing

    KW - Gating step count

    KW - High-level synthesis

    KW - Huddle-based distributed register architecture

    KW - Multi-stage clock gating

    UR - http://www.scopus.com/inward/record.url?scp=84986881492&partnerID=8YFLogxK

    UR - http://www.scopus.com/inward/citedby.url?scp=84986881492&partnerID=8YFLogxK

    U2 - 10.2197/ipsjtsldm.7.74

    DO - 10.2197/ipsjtsldm.7.74

    M3 - Article

    AN - SCOPUS:84986881492

    VL - 7

    SP - 74

    EP - 80

    JO - IPSJ Transactions on System LSI Design Methodology

    JF - IPSJ Transactions on System LSI Design Methodology

    SN - 1882-6687

    ER -