Energy efficient processing engine in LDPC application with high-speed charge recovery logic

Yimeng Zhang, Mengshu Huang, Nan Wang, Satoshi Goto, Tsutomu Yoshihara

    研究成果: Article査読

    1 被引用数 (Scopus)

    抄録

    This paper presents a Processing Engine (PE) which is used in Low Density Parity Codec (LDPC) application with a novel charge-recovery logic called pseudo-NMOS boost logic (pNBL), to achieve high-speed and low power dissipation. pNBL is a high-overdriven and low area consuming charge recovery logic, which belongs to boost logic family. Proposed Processing Engine is used in LDPC circuit to reduce operating power dissipation and increase the processing speed. To demonstrate the performance of proposed PE, a test chip is designed and fabricated with 0.18 2m CMOS technology. Simulation results indicate that proposed PE with pNBL dissipates only 1 pJ/cycle when working at the frequency of 403 MHz, which is only 36% of PE with the conventional static CMOS gates. The measurement results show that the test chip can work as high as 609 MHz with the energy dissipation of 2.1 pJ/cycle.

    本文言語English
    ページ(範囲)341-352
    ページ数12
    ジャーナルJournal of Semiconductor Technology and Science
    12
    3
    DOI
    出版ステータスPublished - 2012 9月

    ASJC Scopus subject areas

    • 電子工学および電気工学
    • 電子材料、光学材料、および磁性材料

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