Energy evaluation for two-level on-chip cache with non-volatile memory on mobile processors

Shota Matsuno, Masashi Tawada, Masao Yanagisawa, Shinji Kimura, Nozomu Togawa, Tadahiko Sugibayashi

研究成果: Conference contribution

1 被引用数 (Scopus)

抄録

As leakage power of traditional SRAM becomes larger, a ratio of static energy in total energy of memory architecture becomes also larger. Non-volatile memory (NVM) has many advantages over SRAM, such as high density, low leakage power, and non-volatility, but consumes too much write energy. In this paper, we evaluate energy consumption of two-level cache using NVM in part on mobile processors and confirm that it effectively reduces energy consumption.

本文言語English
ホスト出版物のタイトル2013 IEEE 10th International Conference on ASIC, ASICON 2013
出版社IEEE Computer Society
ISBN(印刷版)9781467364157
DOI
出版ステータスPublished - 2013 1 1
イベント2013 IEEE 10th International Conference on ASIC, ASICON 2013 - Shenzhen, China
継続期間: 2013 10 282013 10 31

出版物シリーズ

名前Proceedings of International Conference on ASIC
ISSN(印刷版)2162-7541
ISSN(電子版)2162-755X

Other

Other2013 IEEE 10th International Conference on ASIC, ASICON 2013
CountryChina
CityShenzhen
Period13/10/2813/10/31

ASJC Scopus subject areas

  • Hardware and Architecture
  • Electrical and Electronic Engineering

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