Error correction system using stochastic numbers in symmetric channels and z channels

研究成果: Conference contribution

2 被引用数 (Scopus)

抄録

In fields of image processing and neural network, increasing amount of data and complex functions are making circuits precise. This makes errors in circuits relatively large. When upper bits of binary signals flip due to noise, the value will increase or decrease drastically. On the other hand, if stochastic numbers are used, the changes on their values are the same since all the bits have the same weight. Therefore, stochastic computing, a computation method based on stochastic numbers, is attracting interest. Stochastic computing does have error tolerance, but cannot restore the bit stream if the bits are erroneous. Here, we focus on evaluating the error-free value from the bit error rate and the erroneous value. We have proposed a method to correct errors of stochastic numbers by measuring the bit error rate and filtering the values properly in symmetric channels. In this paper, we propose a method that can also correct errors in Z channels as well as symmetric channels. From experimental evaluations, in environment with high bit error rate, this proposal will give a better peak-signal-to-noise ratio compared with a conventional error correction coding.

本文言語English
ホスト出版物のタイトル2019 26th IEEE International Conference on Electronics, Circuits and Systems, ICECS 2019
出版社Institute of Electrical and Electronics Engineers Inc.
ページ578-581
ページ数4
ISBN(電子版)9781728109961
DOI
出版ステータスPublished - 2019 11
イベント26th IEEE International Conference on Electronics, Circuits and Systems, ICECS 2019 - Genoa, Italy
継続期間: 2019 11 272019 11 29

出版物シリーズ

名前2019 26th IEEE International Conference on Electronics, Circuits and Systems, ICECS 2019

Conference

Conference26th IEEE International Conference on Electronics, Circuits and Systems, ICECS 2019
国/地域Italy
CityGenoa
Period19/11/2719/11/29

ASJC Scopus subject areas

  • 電子工学および電気工学
  • 制御と最適化
  • コンピュータ ネットワークおよび通信
  • ハードウェアとアーキテクチャ

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