Error rate decrease through hamming weight change for NAND flash

Chong Zhang; Mengshu Huang; Leona Okamura; Tsutomu Yoshihara

doi:10.1109/ISCIT.2010.5665147

Error rate decrease through hamming weight change for NAND flash

Chong Zhang^*, Mengshu Huang, Leona Okamura, Tsutomu Yoshihara

^*この研究の対応する著者

研究成果: Conference contribution

1 被引用数 (Scopus)

抄録

NAND Flash memory is widely used in recent SoCs. High density NAND Flash requires Error Correcting Code (ECC) mechanism to guarantee data integrity. We propose an efficient ECC model which decrease multi bit errors by considering the Flash memory's characteristic. According to the Flash memory mechanism, 0's error is more likely to happen than 1's error. The proposed error control code counts the number of '1' in a word and inverts all bits to keep the number of 1 is more than that of 0s, which signify a high quantity of Hamming weight. We confirm that the proposed method is not only effective for single error but also dramatically effective for multi bit error.

本文言語	English
ホスト出版物のタイトル	ISCIT 2010 - 2010 10th International Symposium on Communications and Information Technologies
ページ	1079-1082
ページ数	4
DOI	https://doi.org/10.1109/ISCIT.2010.5665147
出版ステータス	Published - 2010
イベント	2010 10th International Symposium on Communications and Information Technologies, ISCIT 2010 - Tokyo 継続期間: 2010 10月 26 → 2010 10月 29

Other

Other	2010 10th International Symposium on Communications and Information Technologies, ISCIT 2010
City	Tokyo
Period	10/10/26 → 10/10/29

ASJC Scopus subject areas

コンピュータネットワークおよび通信
情報システム

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10.1109/ISCIT.2010.5665147

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Zhang, C, Huang, M, Okamura, L & Yoshihara, T 2010, Error rate decrease through hamming weight change for NAND flash. in ISCIT 2010 - 2010 10th International Symposium on Communications and Information Technologies., 5665147, pp. 1079-1082, 2010 10th International Symposium on Communications and Information Technologies, ISCIT 2010, Tokyo, 10/10/26. https://doi.org/10.1109/ISCIT.2010.5665147

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abstract = "NAND Flash memory is widely used in recent SoCs. High density NAND Flash requires Error Correcting Code (ECC) mechanism to guarantee data integrity. We propose an efficient ECC model which decrease multi bit errors by considering the Flash memory's characteristic. According to the Flash memory mechanism, 0's error is more likely to happen than 1's error. The proposed error control code counts the number of '1' in a word and inverts all bits to keep the number of 1 is more than that of 0s, which signify a high quantity of Hamming weight. We confirm that the proposed method is not only effective for single error but also dramatically effective for multi bit error.",

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AB - NAND Flash memory is widely used in recent SoCs. High density NAND Flash requires Error Correcting Code (ECC) mechanism to guarantee data integrity. We propose an efficient ECC model which decrease multi bit errors by considering the Flash memory's characteristic. According to the Flash memory mechanism, 0's error is more likely to happen than 1's error. The proposed error control code counts the number of '1' in a word and inverts all bits to keep the number of 1 is more than that of 0s, which signify a high quantity of Hamming weight. We confirm that the proposed method is not only effective for single error but also dramatically effective for multi bit error.

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T2 - 2010 10th International Symposium on Communications and Information Technologies, ISCIT 2010

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Error rate decrease through hamming weight change for NAND flash

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