Error rate decrease through hamming weight change for NAND flash

Chong Zhang, Mengshu Huang, Leona Okamura, Tsutomu Yoshihara

    研究成果: Conference contribution

    1 被引用数 (Scopus)

    抄録

    NAND Flash memory is widely used in recent SoCs. High density NAND Flash requires Error Correcting Code (ECC) mechanism to guarantee data integrity. We propose an efficient ECC model which decrease multi bit errors by considering the Flash memory's characteristic. According to the Flash memory mechanism, 0's error is more likely to happen than 1's error. The proposed error control code counts the number of '1' in a word and inverts all bits to keep the number of 1 is more than that of 0s, which signify a high quantity of Hamming weight. We confirm that the proposed method is not only effective for single error but also dramatically effective for multi bit error.

    本文言語English
    ホスト出版物のタイトルISCIT 2010 - 2010 10th International Symposium on Communications and Information Technologies
    ページ1079-1082
    ページ数4
    DOI
    出版ステータスPublished - 2010
    イベント2010 10th International Symposium on Communications and Information Technologies, ISCIT 2010 - Tokyo
    継続期間: 2010 10 262010 10 29

    Other

    Other2010 10th International Symposium on Communications and Information Technologies, ISCIT 2010
    CityTokyo
    Period10/10/2610/10/29

    ASJC Scopus subject areas

    • Computer Networks and Communications
    • Information Systems

    フィンガープリント 「Error rate decrease through hamming weight change for NAND flash」の研究トピックを掘り下げます。これらがまとまってユニークなフィンガープリントを構成します。

    引用スタイル