Exact and fast L1 cache configuration simulation for embedded systems with FIFO/PLRU cache replacement policies

Masashi Tawada*, Masao Yanagisawa, Tatsuo Ohtsuki, Nozomu Togawa

*この研究の対応する著者

研究成果

4 被引用数 (Scopus)

抄録

Since target applications in embedded systems are limited, we can optimize its cache configuration. A very fast and exact cache simulation algorithm, CRCB, has been recently proposed. CRCB assumes LRU as a cache replacement policy but FIFO- or PLRU-based cache is often used due to its low hardware cost. This paper proposes exact and fast L1 cache simulation algorithms for PLRU- or FIFO-based caches. First, we prove that CRCB can be applied to FIFO and PLRU. Next, we show several properties for FIFO- and PLRU-based caches and propose their associated cache-simulation speed-up algorithms. Experiments demonstrate that our algorithms run up to 300 times faster than a well-known cache simulator.

本文言語English
ホスト出版物のタイトルProceedings of 2011 International Symposium on VLSI Design, Automation and Test, VLSI-DAT 2011
ページ247-250
ページ数4
DOI
出版ステータスPublished - 2011 6 28
イベント2011 International Symposium on VLSI Design, Automation and Test, VLSI-DAT 2011 - Hsinchu, Taiwan, Province of China
継続期間: 2011 4 252011 4 28

出版物シリーズ

名前Proceedings of 2011 International Symposium on VLSI Design, Automation and Test, VLSI-DAT 2011

Conference

Conference2011 International Symposium on VLSI Design, Automation and Test, VLSI-DAT 2011
国/地域Taiwan, Province of China
CityHsinchu
Period11/4/2511/4/28

ASJC Scopus subject areas

  • ハードウェアとアーキテクチャ
  • 電子工学および電気工学

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