Exact minimization of free bdds and its application to pass-transistor logic optimization

Kazuyoshi Takagi*, Hiroshi Hatakeda, Shinji Kimura, Katsumasa Watanabe

*この研究の対応する著者

研究成果: Article査読

3 被引用数 (Scopus)

抄録

In several design methods for Pass-transistor Logic (PTL) circuits Boolean functions are expressed as OBDDs in decomposed form and then the component OBDDs are directly mapped to PTL cells. The total size of OBDDs (number of nodes) corresponds to the circuit size. In this paper we investigate a method for PTL synthesis based on exact minimization of Free BDDs (FBDDs). FBDDs are well-studied extension of OBDDs with free variable ordering on each path. We present statistics showing that more than 56% of 616126 NPN-equivalence classes of 5-variable Boolean functions have minimum FBDDs with less size than their OBDDs. This result can be used for PTL synthesis as libraries. We also applied the exact minimization algorithm of FBDDs to the minimization of subcircuits in the synthesis for MCNC benchmarks and found up to 5% size reduction.

本文言語English
ページ(範囲)2407-2413
ページ数7
ジャーナルIEICE Transactions on Fundamentals of Electronics, Communications and Computer Sciences
E82-A
11
出版ステータスPublished - 1999
外部発表はい

ASJC Scopus subject areas

  • 信号処理
  • コンピュータ グラフィックスおよびコンピュータ支援設計
  • 電子工学および電気工学
  • 応用数学

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