Experimental 1 Mb cache DRAM with ECC

Mikio Asakura, Yoshio Matsuda, Hideto Hidaka, Yoshinori Tanaka, Kazuyasu Fujishima, Tsutomu Yoshihara

研究成果: Conference contribution

6 被引用数 (Scopus)

抄録

The authors describe a cache DRAM (dynamic RAM) with an ECC (error checking and correcting) circuit. This ECC circuit improves the reliability of the DRAM data. An on-chip cache scheme can provide a high-speed data mapping and relieve access time loss for error correction, thus reducing the average access time. It is shown that a 4-MB main memory system with 32-kB cache memory and 32-b parallel I/Os can be constructed with thirty-two 1-Mb cache DRAM chips or eight 4-Mb cache DRAM chips using the proposed scheme.

本文言語English
ホスト出版物のタイトルSymp VLSI Circuit 1989
編集者 Anon
Place of PublicationPiscataway, NJ, United States
出版社Publ by IEEE
ページ43-44
ページ数2
出版ステータスPublished - 1989
外部発表はい
イベントSymposium on VLSI Circuits 1989 - Kyoto, Japan
継続期間: 1989 5 251989 5 27

Other

OtherSymposium on VLSI Circuits 1989
CityKyoto, Japan
Period89/5/2589/5/27

ASJC Scopus subject areas

  • Engineering(all)

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