抄録
A novel multiple-level storage DRAM (dynamic random-access memory) technique which obtains fairly fast access time is presented. The RAM area, especially the cell-array area, which is highly defect-sensitive, is reduced with this technique. Reasonable yield can thus be achieved. An experimental 1-Mb DRAM has been fabricated, and the 2-bit/cell storage technique has been verified to be suitable for macro-cell or memory-on-logic application.
本文言語 | English |
---|---|
ページ(範囲) | 4.4/1-4 |
ジャーナル | Proceedings of the Custom Integrated Circuits Conference |
出版ステータス | Published - 1988 |
外部発表 | はい |
ASJC Scopus subject areas
- 電子工学および電気工学