A novel multiple-level storage DRAM (dynamic random-access memory) technique which obtains fairly fast access time is presented. The RAM area, especially the cell-array area, which is highly defect-sensitive, is reduced with this technique. Reasonable yield can thus be achieved. An experimental 1-Mb DRAM has been fabricated, and the 2-bit/cell storage technique has been verified to be suitable for macro-cell or memory-on-logic application.
|ジャーナル||Proceedings of the Custom Integrated Circuits Conference|
|出版ステータス||Published - 1988 12 1|
ASJC Scopus subject areas
- Electrical and Electronic Engineering