Experimental 2-bit/cell storage DRAM for macro cell or memory-on-logic application.

Tohru Furuyama*, Takashi Ohsawa, Yousei Nagahama, Hiroto Tanaka, Yohji Watanabe, Tohru Kimura, Kazuyoshi Muraoka, Kenji Natori


研究成果: Conference article査読

3 被引用数 (Scopus)


A novel multiple-level storage DRAM (dynamic random-access memory) technique which obtains fairly fast access time is presented. The RAM area, especially the cell-array area, which is highly defect-sensitive, is reduced with this technique. Reasonable yield can thus be achieved. An experimental 1-Mb DRAM has been fabricated, and the 2-bit/cell storage technique has been verified to be suitable for macro-cell or memory-on-logic application.

ジャーナルProceedings of the Custom Integrated Circuits Conference
出版ステータスPublished - 1988

ASJC Scopus subject areas

  • 電子工学および電気工学


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