Experimental 2-bit/cell storage DRAM for macro cell or memory-on-logic application.

Tohru Furuyama; Takashi Ohsawa; Yousei Nagahama; Hiroto Tanaka; Yohji Watanabe; Tohru Kimura; Kazuyoshi Muraoka; Kenji Natori

Experimental 2-bit/cell storage DRAM for macro cell or memory-on-logic application.

Tohru Furuyama, Takashi Ohsawa, Yousei Nagahama, Hiroto Tanaka, Yohji Watanabe, Tohru Kimura, Kazuyoshi Muraoka, Kenji Natori

研究成果: Conference article › 査読

1 被引用数 (Scopus)

抄録

A novel multiple-level storage DRAM (dynamic random-access memory) technique which obtains fairly fast access time is presented. The RAM area, especially the cell-array area, which is highly defect-sensitive, is reduced with this technique. Reasonable yield can thus be achieved. An experimental 1-Mb DRAM has been fabricated, and the 2-bit/cell storage technique has been verified to be suitable for macro-cell or memory-on-logic application.

本文言語	English
ページ（範囲）	4.4/1-4
ジャーナル	Proceedings of the Custom Integrated Circuits Conference
出版ステータス	Published - 1988 12 1
外部発表	はい

ASJC Scopus subject areas

Electrical and Electronic Engineering

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引用スタイル

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abstract = "A novel multiple-level storage DRAM (dynamic random-access memory) technique which obtains fairly fast access time is presented. The RAM area, especially the cell-array area, which is highly defect-sensitive, is reduced with this technique. Reasonable yield can thus be achieved. An experimental 1-Mb DRAM has been fabricated, and the 2-bit/cell storage technique has been verified to be suitable for macro-cell or memory-on-logic application.",

author = "Tohru Furuyama and Takashi Ohsawa and Yousei Nagahama and Hiroto Tanaka and Yohji Watanabe and Tohru Kimura and Kazuyoshi Muraoka and Kenji Natori",

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T1 - Experimental 2-bit/cell storage DRAM for macro cell or memory-on-logic application.

AU - Furuyama, Tohru

AU - Ohsawa, Takashi

AU - Nagahama, Yousei

AU - Tanaka, Hiroto

AU - Watanabe, Yohji

AU - Kimura, Tohru

AU - Muraoka, Kazuyoshi

AU - Natori, Kenji

PY - 1988/12/1

Y1 - 1988/12/1

N2 - A novel multiple-level storage DRAM (dynamic random-access memory) technique which obtains fairly fast access time is presented. The RAM area, especially the cell-array area, which is highly defect-sensitive, is reduced with this technique. Reasonable yield can thus be achieved. An experimental 1-Mb DRAM has been fabricated, and the 2-bit/cell storage technique has been verified to be suitable for macro-cell or memory-on-logic application.

AB - A novel multiple-level storage DRAM (dynamic random-access memory) technique which obtains fairly fast access time is presented. The RAM area, especially the cell-array area, which is highly defect-sensitive, is reduced with this technique. Reasonable yield can thus be achieved. An experimental 1-Mb DRAM has been fabricated, and the 2-bit/cell storage technique has been verified to be suitable for macro-cell or memory-on-logic application.

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M3 - Conference article

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SP - 4.4/1-4

JO - Proceedings of the Custom Integrated Circuits Conference

JF - Proceedings of the Custom Integrated Circuits Conference

SN - 0886-5930

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