Experimental 256-Mb DRAM with boosted sense-ground scheme

Mikio Asakura, Tsukasa Ooishi, Masaki Tsukude, Shigeki Tomishima, Takahisa Eimori, Hideto Hidaka, Yoshikazu Ohno, Kazutani Arimoto, Kazuyasu Fujishima, Tadashi Nishimura, Tsutomu Yoshihara

研究成果: Article査読

19 被引用数 (Scopus)

抄録

In developing the 256-Mb DRAM, the data retention characteristics must inevitably be improved. In order for DRAM's to remain the semiconductor device with the largest production volume in the 256-Mb era, we must develop a cost effective device with a small chip size and a large process tolerance. In this paper, we propose the BSG (Boosted Sense-Ground) scheme for data retention and FOGOS (FOlded Global and Open Segment bit-line) structure for chip size reduction. We have fabricated an experimental 256-Mb DRAM with these technologies and obtained a chip size of 304 mm2 and a performance of 34 ns access time.

本文言語English
ページ(範囲)1303-1309
ページ数7
ジャーナルIEEE Journal of Solid-State Circuits
29
11
DOI
出版ステータスPublished - 1994 11
外部発表はい

ASJC Scopus subject areas

  • Electrical and Electronic Engineering

フィンガープリント 「Experimental 256-Mb DRAM with boosted sense-ground scheme」の研究トピックを掘り下げます。これらがまとまってユニークなフィンガープリントを構成します。

引用スタイル