Fabrication of nano-sized single-walled carbon nanotube vias for electronic device applications

T. Iwasaki*, R. Morikane, G. Zhong, T. Edura, K. Tsutsui, Y. Wada, H. Kawarada

*この研究の対応する著者

研究成果: Conference contribution

1 被引用数 (Scopus)

抄録

Vertically aligned single-walled carbon nanotubes (SWNTs) were synthesized at a low temperature of 600°C by radical chemical vapor deposition (CVD). For applying this technique to electronic devices, we synthesized SWNTs in nano-sized SiO2 holes to fabricate SWNT-vias, which is expected to be used for multi-layer interconnects and vertically aligned field effect transistors (FET). SWNTs were grown in holes with various sizes and shapes patterned by electron beam lithography. We also show the concept of large area deposition of vertically aligned SWNTs by improved radical CVD system.

本文言語English
ホスト出版物のタイトル2006 NSTI Nanotechnology Conference and Trade Show - NSTI Nanotech 2006 Technical Proceedings
ページ94-97
ページ数4
出版ステータスPublished - 2006 12月 8
イベント2006 NSTI Nanotechnology Conference and Trade Show - NSTI Nanotech 2006 Technical Proceedings - Boston, MA, United States
継続期間: 2006 5月 72006 5月 11

出版物シリーズ

名前2006 NSTI Nanotechnology Conference and Trade Show - NSTI Nanotech 2006 Technical Proceedings
1

Conference

Conference2006 NSTI Nanotechnology Conference and Trade Show - NSTI Nanotech 2006 Technical Proceedings
国/地域United States
CityBoston, MA
Period06/5/706/5/11

ASJC Scopus subject areas

  • 工学(全般)

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