Fault-Tolerant traffic-Aware routing algorithm for 3-d photonic networks-on-chip

Michael Conrad Meyer, Yu Wang, Takahiro Watanabe

研究成果

2 被引用数 (Scopus)

抄録

As the number of cores on a single chip increased, the inter-core communication system quickly became the performance bottleneck. In order to solve the performance and scalability issues of bus-based systems, Network-on-chip (NoC) was proposed. This eventually met its own bottleneck and several technologies sprouted out from NoC research. The most commonly researched upgrade to NoCs was 3D NoCs, which utilized stacked routers to reduce the maximum hop count. Other researchers have looked at alternative transmission mediums, such as photonics. These technologies can be combined to give great performance and power benefits but can be slowed down by congestion in their path-setup phase. In order to solve this issue, we propose a traffic-Aware routing algorithm that can evenly distribute the traffic throughout the chip, all while simultaneously avoiding faulty nodes. The results show that the proposed algorithm was successful in balancing the load across the chip and that the performance costs of the algorithm were mostly offset by the benefits of reducing blocked paths.

本文言語English
ホスト出版物のタイトルProceedings - 2019 IEEE 13th International Symposium on Embedded Multicore/Many-Core Systems-on-Chip, MCSoC 2019
出版社Institute of Electrical and Electronics Engineers Inc.
ページ172-179
ページ数8
ISBN(電子版)9781728148823
DOI
出版ステータスPublished - 2019 10
イベント13th IEEE International Symposium on Embedded Multicore/Many-Core Systems-on-Chip, MCSoC 2019 - Singapore, Singapore
継続期間: 2019 10 12019 10 4

出版物シリーズ

名前Proceedings - 2019 IEEE 13th International Symposium on Embedded Multicore/Many-Core Systems-on-Chip, MCSoC 2019

Conference

Conference13th IEEE International Symposium on Embedded Multicore/Many-Core Systems-on-Chip, MCSoC 2019
国/地域Singapore
CitySingapore
Period19/10/119/10/4

ASJC Scopus subject areas

  • コンピュータ ネットワークおよび通信
  • ハードウェアとアーキテクチャ
  • 電子工学および電気工学
  • 制御と最適化

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