FBC (Floating Body Cell) for Embedded DRAM on SOI

Kazumi Inoh, Tomoaki Shino, Hiroaki Yamada, Hiroomi Nakajima, Yoshihiro Minami, Takashi Yamada, Takashi Ohsawa, Tomoki Higashi, Katsuyuki Fujita, Tamio Ikehashi, Takeshi Kajiyama, Yoshiaki Fukuzumi, Takeshi Hamamoto, Hidemi Ishiuchi

研究成果: Conference article査読

33 被引用数 (Scopus)

抄録

The memory cell characteristics of the FBC (Floating Body Cell) have been experimentally verified by 0.17μm cell array for the first time. The FBC is a one-transistor gain cell, which is a suitable structure for the future embedded DRAM on SOI wafer. The memory cell layout and the process integration have been designed from the viewpoint of the logic process compatibility without sacrificing the data retention characteristics. The salicide process with the poly-Si plug is implemented into the process integration. The most important device characteristics for realizing the FBC is the threshold voltage difference (Δ Vth) of the cell transistor between "1" state and "0" state. The key device parameters in order to enlarge the Δ Vth are experimentally clarified. A Δ Vth of 0.4V has been obtained, which leads to 99.77% function bit yield of 96Kbit ADM (Array Diagnostic Monitor). The retention time of 5sec has been realized at the room temperature.

本文言語English
ページ(範囲)63-64
ページ数2
ジャーナルDigest of Technical Papers - Symposium on VLSI Technology
出版ステータスPublished - 2003 10 1
外部発表はい
イベント2003 Symposium on VLSI Technology - Kyoto, Japan
継続期間: 2003 6 102003 6 12

ASJC Scopus subject areas

  • 電子工学および電気工学

フィンガープリント

「FBC (Floating Body Cell) for Embedded DRAM on SOI」の研究トピックを掘り下げます。これらがまとまってユニークなフィンガープリントを構成します。

引用スタイル