Flexible architecture optimization and ASIC implementation of group signature algorithm using a customized HLS methodology

Sumio Morioka*, Toshiyuki Isshiki, Satoshi Obana, Yuichi Nakamura, Kazue Sako

*この研究の対応する著者

研究成果: Conference contribution

6 被引用数 (Scopus)

抄録

Group signature is one of the main theme in recent digital signature studies. Typical signature algorithm is a combination of more than 70 elliptic curve (ECC), modular (RSA), long-bit integer and hash arithmetic functions. A full H/W IP core is strongly desired for the use of group signature in SoCs in slow-clock and low-power mobile devices and embedded systems. Flexible adjustment of H/W speed and size, depending on different systems and LSI process technologies, is also required. However, for designing and verifying H/W, the group signature algorithm is too complicated to use a standard RTL (Register Transfer Level) design methodology nor any recent HLS (High Level Synthesis). Therefore, we incorporated a two-level behavioral synthesis approach, where an optimized macro-architecture is explored by a custom-made scheduler, after a database of multiple number of microarchitectures are effectively constructed by conventional HLS. We implemented the signature algorithm on a low-cost 0.25um gate-array. The H/W size is approximately 1M gates and our chip can compute a group signature at the equivalent speed (0.135 seconds@100MHz clock) with 3GHz PC S/W, while the power consumption is two orders of magnitude lower (425mW@100MHz).

本文言語English
ホスト出版物のタイトル2011 IEEE International Symposium on Hardware-Oriented Security and Trust, HOST 2011
ページ57-62
ページ数6
DOI
出版ステータスPublished - 2011
外部発表はい
イベント2011 IEEE International Symposium on Hardware-Oriented Security and Trust, HOST 2011 - San Diego, CA, United States
継続期間: 2011 6月 52011 6月 6

出版物シリーズ

名前2011 IEEE International Symposium on Hardware-Oriented Security and Trust, HOST 2011

Conference

Conference2011 IEEE International Symposium on Hardware-Oriented Security and Trust, HOST 2011
国/地域United States
CitySan Diego, CA
Period11/6/511/6/6

ASJC Scopus subject areas

  • ハードウェアとアーキテクチャ
  • 電子工学および電気工学
  • 安全性、リスク、信頼性、品質管理

フィンガープリント

「Flexible architecture optimization and ASIC implementation of group signature algorithm using a customized HLS methodology」の研究トピックを掘り下げます。これらがまとまってユニークなフィンガープリントを構成します。

引用スタイル