FLOOR-PLAN DESIGN SYSTEM FOR LSI LAYOUT.

Takahiro Watanabe*, Hiroshi Baba

*この研究の対応する著者

研究成果: Conference article査読

1 被引用数 (Scopus)

抄録

The authors have presented a floor-plan design system having two planning algorithms and facilities for editing design data and interactively improving floor-plan results. Though user requirements vary for different floor-plans, this system can edit any design data according to the requirements and meet the requirements quickly by presenting prototype floor-plans with evaluation. However, it is necessary not only to select a proper algorithm but also to define an appropriate connectivity. Several connectivities have been investigated to determine whether they could meet such demands or not. Connectivities depending on the Fibonacci number sequence appeared to be appropriate. The worst-case time complexities for practical-sized problems have been determined experimentally.

本文言語English
ページ(範囲)9-12
ページ数4
ジャーナルProceedings - IEEE International Symposium on Circuits and Systems
出版ステータスPublished - 1985 12月 1
外部発表はい

ASJC Scopus subject areas

  • 電子工学および電気工学

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