Floorplan-driven high-level synthesis using volatile/non-volatile registers for hybrid energy-harvesting systems

    研究成果: Conference contribution

    抄録

    In this paper, we propose a floorplan-driven highlevel synthesis algorithm utilizing both volatile and non-volatile registers for hybrid energy-harvesting systems. In our algorithm, we firstly introduce an idea of safety line candidates. Based on them, we perform safety-line (SL) scheduling so that every operation does not cross the safety line candidates and then perform volatile/non-volatile register binding so that all the data crossing the safety line candidates are stored into non-violate registers. We can safely restore all the data and re-start the circuit operation from every safety line candidate, even if the power shut-off occurs while running the circuit. Experimental results show that our algorithm reduces average latency by 30.76% and the average energy consumption by 24.94% compared to the naive algorithm when sufficient energy is given (normal mode). Experimental results also show that our algorithm reduces average latency by 30.58% compared to the naive algorithm by reducing rollback execution if a small amount of energy is given (energy-harvesting mode).

    本文言語English
    ホスト出版物のタイトルProceedings - 2017 IEEE 12th International Conference on ASIC, ASICON 2017
    出版社IEEE Computer Society
    ページ64-67
    ページ数4
    2017-October
    ISBN(電子版)9781509066247
    DOI
    出版ステータスPublished - 2018 1 8
    イベント12th IEEE International Conference on Advanced Semiconductor Integrated Circuits, ASICON 2017 - Guiyang, China
    継続期間: 2017 10 252017 10 28

    Other

    Other12th IEEE International Conference on Advanced Semiconductor Integrated Circuits, ASICON 2017
    国/地域China
    CityGuiyang
    Period17/10/2517/10/28

    ASJC Scopus subject areas

    • ハードウェアとアーキテクチャ
    • 電子工学および電気工学

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