Floorplanning and topology generation for application-specific network-on-chip

Bei Yu, Sheqin Dong, Song Chen, Satoshino Goto

研究成果: Conference contribution

37 引用 (Scopus)

抜粋

Network-on-Chip(NoC) architectures have been proposed as a promising alternative to classical bus-based communication architectures. In this paper, we propose a two phases framework to solve application-specific NoCs topology generation problem. At floorplanning phase, we carry out partition driven floorplanning. At post-floorplanning phase, a heuristic method and a min-cost max-flow algorithm is used to insert switches and network interfaces. Finally, we allocate paths to minimize power consumption. The experimental results show our algorithm is effective for power saving.

元の言語English
ホスト出版物のタイトルProceedings of the Asia and South Pacific Design Automation Conference, ASP-DAC
ページ535-540
ページ数6
DOI
出版物ステータスPublished - 2010
イベント2010 15th Asia and South Pacific Design Automation Conference, ASP-DAC 2010 - Taipei
継続期間: 2010 1 182010 1 21

Other

Other2010 15th Asia and South Pacific Design Automation Conference, ASP-DAC 2010
Taipei
期間10/1/1810/1/21

    フィンガープリント

ASJC Scopus subject areas

  • Electrical and Electronic Engineering
  • Computer Science Applications
  • Computer Graphics and Computer-Aided Design

これを引用

Yu, B., Dong, S., Chen, S., & Goto, S. (2010). Floorplanning and topology generation for application-specific network-on-chip. : Proceedings of the Asia and South Pacific Design Automation Conference, ASP-DAC (pp. 535-540). [5419825] https://doi.org/10.1109/ASPDAC.2010.5419825