Floorplanning and topology generation for application-specific network-on-chip

Bei Yu, Sheqin Dong, Song Chen, Satoshino Goto

研究成果: Conference contribution

37 引用 (Scopus)

抄録

Network-on-Chip(NoC) architectures have been proposed as a promising alternative to classical bus-based communication architectures. In this paper, we propose a two phases framework to solve application-specific NoCs topology generation problem. At floorplanning phase, we carry out partition driven floorplanning. At post-floorplanning phase, a heuristic method and a min-cost max-flow algorithm is used to insert switches and network interfaces. Finally, we allocate paths to minimize power consumption. The experimental results show our algorithm is effective for power saving.

元の言語English
ホスト出版物のタイトルProceedings of the Asia and South Pacific Design Automation Conference, ASP-DAC
ページ535-540
ページ数6
DOI
出版物ステータスPublished - 2010
イベント2010 15th Asia and South Pacific Design Automation Conference, ASP-DAC 2010 - Taipei
継続期間: 2010 1 182010 1 21

Other

Other2010 15th Asia and South Pacific Design Automation Conference, ASP-DAC 2010
Taipei
期間10/1/1810/1/21

Fingerprint

Topology
Heuristic methods
Interfaces (computer)
Electric power utilization
Switches
Communication
Costs
Network-on-chip

ASJC Scopus subject areas

  • Electrical and Electronic Engineering
  • Computer Science Applications
  • Computer Graphics and Computer-Aided Design

これを引用

Yu, B., Dong, S., Chen, S., & Goto, S. (2010). Floorplanning and topology generation for application-specific network-on-chip. : Proceedings of the Asia and South Pacific Design Automation Conference, ASP-DAC (pp. 535-540). [5419825] https://doi.org/10.1109/ASPDAC.2010.5419825

Floorplanning and topology generation for application-specific network-on-chip. / Yu, Bei; Dong, Sheqin; Chen, Song; Goto, Satoshino.

Proceedings of the Asia and South Pacific Design Automation Conference, ASP-DAC. 2010. p. 535-540 5419825.

研究成果: Conference contribution

Yu, B, Dong, S, Chen, S & Goto, S 2010, Floorplanning and topology generation for application-specific network-on-chip. : Proceedings of the Asia and South Pacific Design Automation Conference, ASP-DAC., 5419825, pp. 535-540, 2010 15th Asia and South Pacific Design Automation Conference, ASP-DAC 2010, Taipei, 10/1/18. https://doi.org/10.1109/ASPDAC.2010.5419825
Yu B, Dong S, Chen S, Goto S. Floorplanning and topology generation for application-specific network-on-chip. : Proceedings of the Asia and South Pacific Design Automation Conference, ASP-DAC. 2010. p. 535-540. 5419825 https://doi.org/10.1109/ASPDAC.2010.5419825
Yu, Bei ; Dong, Sheqin ; Chen, Song ; Goto, Satoshino. / Floorplanning and topology generation for application-specific network-on-chip. Proceedings of the Asia and South Pacific Design Automation Conference, ASP-DAC. 2010. pp. 535-540
@inproceedings{a8be9bb867fa43e783f0f83c2b31c31c,
title = "Floorplanning and topology generation for application-specific network-on-chip",
abstract = "Network-on-Chip(NoC) architectures have been proposed as a promising alternative to classical bus-based communication architectures. In this paper, we propose a two phases framework to solve application-specific NoCs topology generation problem. At floorplanning phase, we carry out partition driven floorplanning. At post-floorplanning phase, a heuristic method and a min-cost max-flow algorithm is used to insert switches and network interfaces. Finally, we allocate paths to minimize power consumption. The experimental results show our algorithm is effective for power saving.",
author = "Bei Yu and Sheqin Dong and Song Chen and Satoshino Goto",
year = "2010",
doi = "10.1109/ASPDAC.2010.5419825",
language = "English",
isbn = "9781424457656",
pages = "535--540",
booktitle = "Proceedings of the Asia and South Pacific Design Automation Conference, ASP-DAC",

}

TY - GEN

T1 - Floorplanning and topology generation for application-specific network-on-chip

AU - Yu, Bei

AU - Dong, Sheqin

AU - Chen, Song

AU - Goto, Satoshino

PY - 2010

Y1 - 2010

N2 - Network-on-Chip(NoC) architectures have been proposed as a promising alternative to classical bus-based communication architectures. In this paper, we propose a two phases framework to solve application-specific NoCs topology generation problem. At floorplanning phase, we carry out partition driven floorplanning. At post-floorplanning phase, a heuristic method and a min-cost max-flow algorithm is used to insert switches and network interfaces. Finally, we allocate paths to minimize power consumption. The experimental results show our algorithm is effective for power saving.

AB - Network-on-Chip(NoC) architectures have been proposed as a promising alternative to classical bus-based communication architectures. In this paper, we propose a two phases framework to solve application-specific NoCs topology generation problem. At floorplanning phase, we carry out partition driven floorplanning. At post-floorplanning phase, a heuristic method and a min-cost max-flow algorithm is used to insert switches and network interfaces. Finally, we allocate paths to minimize power consumption. The experimental results show our algorithm is effective for power saving.

UR - http://www.scopus.com/inward/record.url?scp=77951241271&partnerID=8YFLogxK

UR - http://www.scopus.com/inward/citedby.url?scp=77951241271&partnerID=8YFLogxK

U2 - 10.1109/ASPDAC.2010.5419825

DO - 10.1109/ASPDAC.2010.5419825

M3 - Conference contribution

AN - SCOPUS:77951241271

SN - 9781424457656

SP - 535

EP - 540

BT - Proceedings of the Asia and South Pacific Design Automation Conference, ASP-DAC

ER -