Floorplanning driven network-on-chip synthesis for 3-D SoCs

Wei Zhong, Song Chen, Fei Ma, Takeshi Yoshimura, Satoshi Goto

研究成果: Conference contribution

12 引用 (Scopus)

抜粋

1 As technology advances, 3-D stacking of silicon layers is emerging as a promising approach to address the integration challenges faced by current System-on-Chips (SoCs). Designing efficient Network-on-Chips (NoCs) is necessary to handle the 3-D interconnect complexity. In this paper, we present a four-stage synthesis approach to determine the power-performance efficient 3-D NoC topology for the application. First, we propose an algorithm to explore optimal clustering of cores during 3-D floorplanning. Then, an Integer Linear Programming (ILP) algorithm is proposed to place switches and network interfaces on the 3-D floorplan. Thirdly, a power and timing aware path allocation algorithm is carried out to determine the connectivity across different switches. Last, a min-cost max-flow based algorithm is proposed for Through-Silicon Via (TSV) assignment to minimize the link power consumption. Experimental results show the effectiveness of the proposed algorithm.

元の言語English
ホスト出版物のタイトルProceedings - IEEE International Symposium on Circuits and Systems
ページ1203-1206
ページ数4
DOI
出版物ステータスPublished - 2011
イベント2011 IEEE International Symposium of Circuits and Systems, ISCAS 2011 - Rio de Janeiro
継続期間: 2011 5 152011 5 18

Other

Other2011 IEEE International Symposium of Circuits and Systems, ISCAS 2011
Rio de Janeiro
期間11/5/1511/5/18

ASJC Scopus subject areas

  • Electrical and Electronic Engineering

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  • これを引用

    Zhong, W., Chen, S., Ma, F., Yoshimura, T., & Goto, S. (2011). Floorplanning driven network-on-chip synthesis for 3-D SoCs. : Proceedings - IEEE International Symposium on Circuits and Systems (pp. 1203-1206). [5937785] https://doi.org/10.1109/ISCAS.2011.5937785