Floorplanning for high utilization of heterogeneous FPGAs

Nan Liu, Song Chen, Takeshi Yoshimura

研究成果: Article査読

1 被引用数 (Scopus)

抄録

Heterogeneous resources such as configurable logic blocks (CLBs), multiplier blocks (MULs) and RAM blocks (RAMs) where millions of logic gates are included have been added to field programmable gate arrays (FPGAs). The fixed-outline floorplanning used by the existing methods always has a big penalty item in the objective function to ensure all the modules are placed in the specified chip region, which maybe greatly degrade the wirelength. This paper presents a three-phase floorplanning method for heterogeneous FPGAs. First, a non-slicing free-outline floorplanning method is used to optimize the wirelength, however, in this phase, the satisfaction of resource requirements from functional modules might fail. Second, a min-cost-max-flow algorithm is used to tune the assignment of CLBs to functional modules, and assign contiguous regions to each module so that all the functional modules satisfy CLB requirements. Finally, the MULs and RAMs are allocated to modules by a network flow model. CLBs hold the maximum quantity among all the resources. Therefore, making a high utilization of them means an enhancement of the FPGA densities. The proposed method can improve the utilization of CLBs, hence, much larger circuits could be mapped to the same FPGA chip. The results show that about 7-85% wirelength reduction is obtained, and CLB utilization is improved by about 25%.

本文言語English
ページ(範囲)1529-1537
ページ数9
ジャーナルIEICE Transactions on Fundamentals of Electronics, Communications and Computer Sciences
E95-A
9
DOI
出版ステータスPublished - 2012 9

ASJC Scopus subject areas

  • 電子工学および電気工学
  • コンピュータ グラフィックスおよびコンピュータ支援設計
  • 応用数学
  • 信号処理

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