Floorplanning with constraint extraction based on interconnecting information analysis

Jiayi Liu, Sheqin Dong, Xianlong Hong, Satoshi Goto

研究成果: Conference contribution

1 被引用数 (Scopus)

抄録

After the phase of high level synthesis, a lot of design information is hidden for the floorplanning process. As a result, the floorplanning process which is only aiming at decreasing area and wirelength may cause design failure for the circuits, because of ignoring some hidden constraints. In this paper, we propose a method to extract some geometric constraints based on interconnecting information analysis. And a new floorplanning algorithm with CBL representation which can handle these constraints is also proposed. And the final experimental results prove the effectiveness of our method.

本文言語English
ホスト出版物のタイトルASICON 2007 - 2007 7th International Conference on ASIC Proceeding
ページ1084-1087
ページ数4
DOI
出版ステータスPublished - 2007
イベント2007 7th International Conference on ASIC, ASICON 2007 - Guilin
継続期間: 2007 10 262007 10 29

Other

Other2007 7th International Conference on ASIC, ASICON 2007
CityGuilin
Period07/10/2607/10/29

ASJC Scopus subject areas

  • Hardware and Architecture
  • Electrical and Electronic Engineering

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