Folding of logic functions and its application to look up table compaction

Shinji Kimura*, Takashi Horiyama, Masaki Nakanishi, Hirotsugu Kajihara

*この研究の対応する著者

研究成果: Conference article査読

11 被引用数 (Scopus)

抄録

The paper describes the folding method of logic functions to reduce the size of memories for keeping the functions. The folding is based on the relation of fractions of logic functions. We show that the fractions of the full adder function have the bit-wise NOT relation and the bit-wise OR relation, and that the memory size becomes half (8-bit). We propose a new 3-1 LUT with the folding mechanisms which can implement a full adder with one LUT. A fast carry propagation line is introduced for a multi-bit addition. The folding and fast carry propagation mechanisms are shown to be useful to implement other multi-bit operations and general 4 input functions without extra hardware resources. The paper shows the reduction of the area consumption when using our LUTs compared to the case using 4-1 LUTs on several benchmark circuits.

本文言語English
ページ(範囲)694-697
ページ数4
ジャーナルIEEE/ACM International Conference on Computer-Aided Design, Digest of Technical Papers
DOI
出版ステータスPublished - 2002
イベントIEEE/ACM International Conference on Computer Aided Design (ICCAD) - San Jose, CA, United States
継続期間: 2002 11月 102002 11月 14

ASJC Scopus subject areas

  • ソフトウェア
  • コンピュータ サイエンスの応用
  • コンピュータ グラフィックスおよびコンピュータ支援設計

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