The paper describes the folding method of logic functions to reduce the size of memories for keeping the functions. The folding is based on the relation of fractions of logic functions. We show that the fractions of the full adder function have the bit-wise NOT relation and the bit-wise OR relation, and that the memory size becomes half (8-bit). We propose a new 3-1 LUT with the folding mechanisms which can implement a full adder with one LUT. A fast carry propagation line is introduced for a multi-bit addition. The folding and fast carry propagation mechanisms are shown to be useful to implement other multi-bit operations and general 4 input functions without extra hardware resources. The paper shows the reduction of the area consumption when using our LUTs compared to the case using 4-1 LUTs on several benchmark circuits.
|ジャーナル||IEEE/ACM International Conference on Computer-Aided Design, Digest of Technical Papers|
|出版ステータス||Published - 2002|
|イベント||IEEE/ACM International Conference on Computer Aided Design (ICCAD) - San Jose, CA, United States|
継続期間: 2002 11月 10 → 2002 11月 14
ASJC Scopus subject areas
- コンピュータ サイエンスの応用
- コンピュータ グラフィックスおよびコンピュータ支援設計