FPGA implementation of high frame rate and ultra-low delay tracking with local-search based block matching

Tingting Hu, Hong Wu, Takeshi Ikenaga

研究成果: Conference contribution

2 被引用数 (Scopus)

抄録

As more and more human-machine interactive applications call for higher frame rate and lower delay to get a better experience, there is an inevitable need for high frame rate and ultra-low delay image processing system. Current existing works based on vision chip target on video with simple patterns or simple shapes in order to get a higher speed, which is reasonable in the first trial of this new field. However, more complicated system is required for real-life applications. This paper proposes a KLT (Kanade-Lucas-Tomasi) based tracking system with high frame rate and ultra-low delay, implemented on FPGA board. And based on the framework of KLT, local maximum neighboring check, local-search based SAD (Sum of Absolute Difference) block matching and coordinate-addressed feature storage are proposed to localize the whole algorithm. In a broader framework, the whole system is made parallelized and pipelined in order to get a high throughput which can meet the high frame rate and ultra-low delay system's demand. Evaluation results show that the proposed hardware system can work at 784fps and 0.762ms delay with resolution of 640×480.

本文言語English
ホスト出版物のタイトルProceedings - 2017 International Conference on Machine Vision and Information Technology, CMVIT 2017
出版社Institute of Electrical and Electronics Engineers Inc.
ページ93-98
ページ数6
ISBN(電子版)9781509049936
DOI
出版ステータスPublished - 2017 3 14
イベント2017 International Conference on Machine Vision and Information Technology, CMVIT 2017 - Singapore, Singapore
継続期間: 2017 2 172017 2 19

Other

Other2017 International Conference on Machine Vision and Information Technology, CMVIT 2017
CountrySingapore
CitySingapore
Period17/2/1717/2/19

ASJC Scopus subject areas

  • Computer Science Applications
  • Signal Processing
  • Computer Vision and Pattern Recognition

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