### 抄録

This paper addresses parallel prefix adder synthesis which aims at minimizing the total switching activity under bitwise timing constraints. This problem is treated as synthesis of prefix graphs which represent global structures of parallel prefix adders at technology-independent level. An approach for timing-driven area minimization of prefix graphs has been already proposed which first finds the exact minimum solution on a specific subset of prefix graphs by dynamic programming, then restructures the result for further reduction by removing restrictions on the subset. In this paper, a switching cost of each node of a prefix graph is defined, and an approach to minimize the total switching cost is presented where our area minimization algorithm is extended to be able to calculate the switching cost using Ordered Binary-Decision Diagrams (OBDDs). Furthermore, a heuristic is integrated which estimates the effect of the restructuring phase in the dynamic programming phase, to improve the robustness of our algorithm under severe timing constraints. Through a series of experiments, the proposed approach is shown to be effective especially when timing constraints are not tight and/or there are comparably a large number of nodes with very low switching costs.

元の言語 | English |
---|---|

ページ（範囲） | 212-221 |

ページ数 | 10 |

ジャーナル | IPSJ Transactions on System LSI Design Methodology |

巻 | 2 |

DOI | |

出版物ステータス | Published - 2009 |

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### ASJC Scopus subject areas

- Electrical and Electronic Engineering
- Computer Science Applications

### これを引用

*IPSJ Transactions on System LSI Design Methodology*,

*2*, 212-221. https://doi.org/10.2197/ipsjtsldm.2.212

**Framework for parallel prefix adder synthesis considering switching activities.** / Matsunaga, Taeko; Kimura, Shinji; Matsunaga, Yusuke.

研究成果: Article

*IPSJ Transactions on System LSI Design Methodology*, 巻. 2, pp. 212-221. https://doi.org/10.2197/ipsjtsldm.2.212

}

TY - JOUR

T1 - Framework for parallel prefix adder synthesis considering switching activities

AU - Matsunaga, Taeko

AU - Kimura, Shinji

AU - Matsunaga, Yusuke

PY - 2009

Y1 - 2009

N2 - This paper addresses parallel prefix adder synthesis which aims at minimizing the total switching activity under bitwise timing constraints. This problem is treated as synthesis of prefix graphs which represent global structures of parallel prefix adders at technology-independent level. An approach for timing-driven area minimization of prefix graphs has been already proposed which first finds the exact minimum solution on a specific subset of prefix graphs by dynamic programming, then restructures the result for further reduction by removing restrictions on the subset. In this paper, a switching cost of each node of a prefix graph is defined, and an approach to minimize the total switching cost is presented where our area minimization algorithm is extended to be able to calculate the switching cost using Ordered Binary-Decision Diagrams (OBDDs). Furthermore, a heuristic is integrated which estimates the effect of the restructuring phase in the dynamic programming phase, to improve the robustness of our algorithm under severe timing constraints. Through a series of experiments, the proposed approach is shown to be effective especially when timing constraints are not tight and/or there are comparably a large number of nodes with very low switching costs.

AB - This paper addresses parallel prefix adder synthesis which aims at minimizing the total switching activity under bitwise timing constraints. This problem is treated as synthesis of prefix graphs which represent global structures of parallel prefix adders at technology-independent level. An approach for timing-driven area minimization of prefix graphs has been already proposed which first finds the exact minimum solution on a specific subset of prefix graphs by dynamic programming, then restructures the result for further reduction by removing restrictions on the subset. In this paper, a switching cost of each node of a prefix graph is defined, and an approach to minimize the total switching cost is presented where our area minimization algorithm is extended to be able to calculate the switching cost using Ordered Binary-Decision Diagrams (OBDDs). Furthermore, a heuristic is integrated which estimates the effect of the restructuring phase in the dynamic programming phase, to improve the robustness of our algorithm under severe timing constraints. Through a series of experiments, the proposed approach is shown to be effective especially when timing constraints are not tight and/or there are comparably a large number of nodes with very low switching costs.

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U2 - 10.2197/ipsjtsldm.2.212

DO - 10.2197/ipsjtsldm.2.212

M3 - Article

AN - SCOPUS:79954459222

VL - 2

SP - 212

EP - 221

JO - IPSJ Transactions on System LSI Design Methodology

JF - IPSJ Transactions on System LSI Design Methodology

SN - 1882-6687

ER -