A novel high-speed low-power 64K dynamic RAM with enough margin has been attained using a double polysilicon and 3- mu m process technologies. To obtain a low soft error rate below 1 multiplied by 10** minus **6 errors per device hour without sacrificing the high-speed and low-power operation, some novel approaches are proposed in the designs. Fully boosted circuits and the Hi-C cell structure with polysilicon bit line are designed to increase the margin of the single 5-v power supply 64K dynamic RAM. The fabricated device provides a typical access time of 90 ns and an operating power of 190 mw at 25 degree C. The design features of the automatic and self-refresh functions on the same chip are described. 11 refs.
|ジャーナル||IEEE Journal of Solid-State Circuits|
|出版ステータス||Published - 1981 10|
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