GAAS 1-KBIT STATIC RAM WITH A SHALLOW RECESSED-GATE STRUCTURE FET.

Satoshi Takano; Noriyuki Tanino; Tsutomu Yoshihara; Yasuo Mitsui; Kazuo Nishitani

GAAS 1-KBIT STATIC RAM WITH A SHALLOW RECESSED-GATE STRUCTURE FET.

Satoshi Takano^*, Noriyuki Tanino, Tsutomu Yoshihara, Yasuo Mitsui, Kazuo Nishitani

^*この研究の対応する著者

研究成果: Article › 査読

7 被引用数 (Scopus)

抄録

A novel GaAs FET structure has been developed. In order to decrease the source resistance and gate capacitance a shallow n** plus implanted layer was formed between the gate and the source/drain region; then the gate region was slightly recessed. This FET has a high transconductance, low-source resistance, small gate capacitance, and small deviation of threshold voltage. It is suitable for high-speed GaAs LSIs. A 1-kbit static RAM has been designed and fabricated with this FET structure and an access time of 3. 8 ns with 38-mW power dissipation has been obtained.

本文言語	English
ページ（範囲）	1135-1139
ページ数	5
ジャーナル	IEEE Transactions on Electron Devices
巻	ED-32
号	6
出版ステータス	Published - 1985 6月
外部発表	はい

ASJC Scopus subject areas

電子工学および電気工学
物理学および天文学（その他）

他のファイルとリンク

引用スタイル

@article{6e170822e27f41c8980ffed34c370743,

title = "GAAS 1-KBIT STATIC RAM WITH A SHALLOW RECESSED-GATE STRUCTURE FET.",

abstract = "A novel GaAs FET structure has been developed. In order to decrease the source resistance and gate capacitance a shallow n** plus implanted layer was formed between the gate and the source/drain region; then the gate region was slightly recessed. This FET has a high transconductance, low-source resistance, small gate capacitance, and small deviation of threshold voltage. It is suitable for high-speed GaAs LSIs. A 1-kbit static RAM has been designed and fabricated with this FET structure and an access time of 3. 8 ns with 38-mW power dissipation has been obtained.",

author = "Satoshi Takano and Noriyuki Tanino and Tsutomu Yoshihara and Yasuo Mitsui and Kazuo Nishitani",

year = "1985",

month = jun,

language = "English",

volume = "ED-32",

pages = "1135--1139",

journal = "IEEE Transactions on Electron Devices",

issn = "0018-9383",

publisher = "Institute of Electrical and Electronics Engineers Inc.",

number = "6",

}

TY - JOUR

T1 - GAAS 1-KBIT STATIC RAM WITH A SHALLOW RECESSED-GATE STRUCTURE FET.

AU - Takano, Satoshi

AU - Tanino, Noriyuki

AU - Yoshihara, Tsutomu

AU - Mitsui, Yasuo

AU - Nishitani, Kazuo

PY - 1985/6

Y1 - 1985/6

N2 - A novel GaAs FET structure has been developed. In order to decrease the source resistance and gate capacitance a shallow n** plus implanted layer was formed between the gate and the source/drain region; then the gate region was slightly recessed. This FET has a high transconductance, low-source resistance, small gate capacitance, and small deviation of threshold voltage. It is suitable for high-speed GaAs LSIs. A 1-kbit static RAM has been designed and fabricated with this FET structure and an access time of 3. 8 ns with 38-mW power dissipation has been obtained.

AB - A novel GaAs FET structure has been developed. In order to decrease the source resistance and gate capacitance a shallow n** plus implanted layer was formed between the gate and the source/drain region; then the gate region was slightly recessed. This FET has a high transconductance, low-source resistance, small gate capacitance, and small deviation of threshold voltage. It is suitable for high-speed GaAs LSIs. A 1-kbit static RAM has been designed and fabricated with this FET structure and an access time of 3. 8 ns with 38-mW power dissipation has been obtained.

UR - http://www.scopus.com/inward/record.url?scp=0022082038&partnerID=8YFLogxK

UR - http://www.scopus.com/inward/citedby.url?scp=0022082038&partnerID=8YFLogxK

M3 - Article

AN - SCOPUS:0022082038

VL - ED-32

SP - 1135

EP - 1139

JO - IEEE Transactions on Electron Devices

JF - IEEE Transactions on Electron Devices

SN - 0018-9383

IS - 6

ER -

GAAS 1-KBIT STATIC RAM WITH A SHALLOW RECESSED-GATE STRUCTURE FET.

抄録

ASJC Scopus subject areas

他のファイルとリンク

フィンガープリント

引用スタイル