抜粋
A novel GaAs FET structure has been developed. In order to decrease the source resistance and gate capacitance a shallow n** plus implanted layer was formed between the gate and the source/drain region; then the gate region was slightly recessed. This FET has a high transconductance, low-source resistance, small gate capacitance, and small deviation of threshold voltage. It is suitable for high-speed GaAs LSIs. A 1-kbit static RAM has been designed and fabricated with this FET structure and an access time of 3. 8 ns with 38-mW power dissipation has been obtained.
| 元の言語 | English |
|---|---|
| ページ（範囲） | 1135-1139 |
| ページ数 | 5 |
| ジャーナル | IEEE Transactions on Electron Devices |
| 巻 | ED-32 |
| 発行部数 | 6 |
| 出版物ステータス | Published - 1985 6 |
| 外部発表 | Yes |
ASJC Scopus subject areas
- Electrical and Electronic Engineering
- Physics and Astronomy (miscellaneous)
フィンガープリント GAAS 1-KBIT STATIC RAM WITH A SHALLOW RECESSED-GATE STRUCTURE FET.' の研究トピックを掘り下げます。これらはともに一意のフィンガープリントを構成します。
これを引用
Takano, S., Tanino, N., Yoshihara, T., Mitsui, Y., & Nishitani, K. (1985). GAAS 1-KBIT STATIC RAM WITH A SHALLOW RECESSED-GATE STRUCTURE FET. IEEE Transactions on Electron Devices, ED-32(6), 1135-1139.