Gate electrode engineering by control of grain growth for high performance and high reliable 0.18 μm dual gate CMOS

S. Shimizu*, T. Kuroi, H. Sayama, A. Furukawa, Y. Nishida, Y. Inoue, M. Inuishi, T. Nishimura

*この研究の対応する著者

研究成果: Conference article査読

11 被引用数 (Scopus)

抄録

Advanced gate electrode engineering is demonstrated to overcome the key issues of dual gate CMOS with thin gate oxide film. Using the small-grain-size polysilicon for the gate electrode, not only the suppression of gate depletion but also the stability of threshold voltage can be achieved as well as the improvement of the gate oxide integrity. Furthermore this successful implementation into 0.18 μm in CMOS is demonstrated with high performance and high reliability.

本文言語English
ページ(範囲)107-108
ページ数2
ジャーナルDigest of Technical Papers - Symposium on VLSI Technology
出版ステータスPublished - 1997 1月 1
外部発表はい
イベントProceedings of the 1997 Symposium on VLSI Technology - Kyoto, Jpn
継続期間: 1997 6月 101997 6月 12

ASJC Scopus subject areas

  • 電子工学および電気工学

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