Gate electrode engineering by control of grain growth for high performance and high reliable 0.18 μm dual gate CMOS

S. Shimizu^*, T. Kuroi, H. Sayama, A. Furukawa, Y. Nishida, Y. Inoue, M. Inuishi, T. Nishimura

^*この研究の対応する著者

研究成果: Conference article › 査読